{"record":{"id":"00ec56b918fcdb54","repo":"embassy-rs/embassy","slug":"ic2-is-not-ready-to-be-selected-as-system-clock-so","errorCode":null,"errorMessage":"IC2 is not ready to be selected as system clock source (make sure that IC6 and IC11 were configured as well)","messagePattern":"IC2 is not ready to be selected as system clock source \\(make sure that IC6 and IC11 were configured as well\\)","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/rcc/n6.rs","lineNumber":373,"sourceCode":"        CpuClk::Hsi if !RCC.sr().read().hsirdy() => panic!(\"HSI is not ready to be selected as CPU clock source\"),\n        CpuClk::Msi if !RCC.sr().read().msirdy() => panic!(\"MSI is not ready to be selected as CPU clock source\"),\n        CpuClk::Hse if !RCC.sr().read().hserdy() => panic!(\"HSE is not ready to be selected as CPU clock source\"),\n        CpuClk::Ic1 if !ic_enabled(1) => panic!(\"IC1 is not ready to be selected as CPU clock source\"),\n        _ => {}\n    }\n    // set source\n    let cpusw = Cpusw::from_bits(config.cpu.to_bits());\n    RCC.cfgr().modify(|w| w.set_cpusw(cpusw));\n    // wait for changes to take effect\n    while RCC.cfgr().read().cpusws() != Cpusws::from_bits(config.cpu.to_bits()) {}\n\n    // sysclk\n    debug!(\"configuring sysclk\");\n    match config.sys {\n        SysClk::Hsi if !RCC.sr().read().hsirdy() => panic!(\"HSI is not ready to be selected as system clock source\"),\n        SysClk::Msi if !RCC.sr().read().msirdy() => panic!(\"MSI is not ready to be selected as system clock source\"),\n        SysClk::Hse if !RCC.sr().read().hserdy() => panic!(\"HSE is not ready to be selected as system clock source\"),\n        SysClk::Ic2 if !ic_enabled(2) || !ic_enabled(6) || !ic_enabled(11) => panic!(\n            \"IC2 is not ready to be selected as system clock source (make sure that IC6 and IC11 were configured as well)\"\n        ),\n        _ => {}\n    }\n    // switch the system bus clock\n    let syssw = Syssw::from_bits(config.sys.to_bits());\n    RCC.cfgr().modify(|w| w.set_syssw(syssw));\n    // wait for changes to be applied\n    while RCC.cfgr().read().syssws() != Syssws::from_bits(config.sys.to_bits()) {}\n\n    // decreasing dividers\n    debug!(\"configuring decreasing pclk dividers\");\n    RCC.cfgr2().modify(|w| {\n        if config.ahb < w.hpre() {\n            debug!(\"  - AHB\");\n            w.set_hpre(config.ahb);\n        }\n        if config.apb1 < w.ppre1() {","sourceCodeStart":355,"sourceCodeEnd":391,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/rcc/n6.rs#L355-L391","documentation":"This panic comes from embassy-stm32's STM32N6 RCC init when the requested system clock source is IC2 (an internal clock multiplexer output). IC2 is fed by IC6 and IC11, so the driver refuses to switch sysclk to IC2 unless intermediate clock units IC6 and IC11 have already been configured and enabled (ic_enabled checks). It fails fast rather than switching to a dead clock.","triggerScenarios":"Calling rcc init/init_config with SysClk::Ic2 while RCC.sr() reports IC6 or IC11 (or IC2 itself) not enabled — i.e. the IC6/IC11 intermediate clock units were never set up in the same clock tree configuration.","commonSituations":"Hand-writing a clock tree config for STM32N6 and selecting IC2 as sysclk without configuring the full IC6->IC11 chain; copying a clock config from another STM32 family where IC2 did not need intermediate units; typos or partially filled ClockTree structs in generated config code.","solutions":["Configure IC6 and IC11 in the rcc config so they feed IC2 before selecting SysClk::Ic2 as the system clock source","Or select a directly-ready source (SysClk::Hsi, SysClk::Msi, SysClk::Hse) instead of IC2","Ensure the oscillator feeding the IC chain (e.g. PLL or HSE) is enabled first so ic_enabled(6)/ic_enabled(11) return true"],"exampleFix":"// before\nconfig.sys = SysClk::Ic2; // IC6/IC11 not configured\n// after\nconfig.ic6 = Some(Ic6Config::from(pll1_p_output));\nconfig.ic11 = Some(Ic11Config::from(hse_output));\nconfig.sys = SysClk::Ic2;","handlingStrategy":"validation","validationCode":"// STM32N6, before init with SysClk::Ic2\nfn ic2_chain_ready() -> bool {\n    let sr = unsafe { (*stm32_metapac::RCC::ptr()).sr().read() };\n    // IC2 requires IC6 and IC11 enabled\n    sr.ic6rdy() && sr.ic11rdy()\n}\nassert!(ic2_chain_ready(), \"configure IC6/IC11 before selecting IC2 as sysclk\");","typeGuard":"fn is_ic2_configurable(cfg: &Config) -> bool {\n    cfg.ic6.is_some() && cfg.ic11.is_some()\n}","tryCatchPattern":"// panics are fatal on embedded; wrap init in a halting hook instead\ndef_modinit_handler(|| {\n    // log via UART/RTT, then safe-reset\n    system_reset();\n});","preventionTips":["Build the full IC6 -> IC11 -> IC2 chain in the clock config, never IC2 alone","Prefer directly-ready sources (HSI/MSI/HSE) unless you specifically need IC2","Start from a known-good generated clock config for your exact N6 board"],"tags":["rust","embedded","rcc","clock-config","stm32n6"],"backgroundTag":"invalid-config-value","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}