{"record":{"id":"1252942f2a3ad7b6","repo":"embassy-rs/embassy","slug":"reserved-pll-source-not-allowed","errorCode":null,"errorMessage":"reserved PLL source not allowed","messagePattern":"reserved PLL source not allowed","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/rcc/n6.rs","lineNumber":747,"sourceCode":"    cfgr1.modify(|w| w.set_pllbyp(false));\n}\n\nfn pll_output(pll_config: Option<Pll>, input: &PllInput) -> PllOutput {\n    match pll_config {\n        Some(Pll::Oscillator {\n            source,\n            divm,\n            fractional: _,\n            divn,\n            divp1,\n            divp2,\n        }) => {\n            let in_clk = match source {\n                Pllsel::Hsi => unwrap!(input.hsi),\n                Pllsel::Msi => unwrap!(input.msi),\n                Pllsel::Hse => unwrap!(input.hse),\n                Pllsel::I2sCkin => unwrap!(input.i2s_ckin),\n                _ => panic!(\"reserved PLL source not allowed\"),\n            };\n            let m = divm.to_bits() as u32;\n            let n = divn as u32;\n            let p1 = divp1.to_bits() as u32;\n            let p2 = divp2.to_bits() as u32;\n\n            PllOutput {\n                divm: Some(Hertz(m)),\n                divn: Some(Hertz(n)),\n                divp1: Some(Hertz(p1)),\n                divp2: Some(Hertz(p2)),\n                output: Some(Hertz(in_clk.0 / m * n / p1 / p2)),\n            }\n        }\n        Some(Pll::Bypass { source }) => {\n            let in_clk = match source {\n                Pllsel::Hsi => unwrap!(input.hsi),\n                Pllsel::Msi => unwrap!(input.msi),","sourceCodeStart":729,"sourceCodeEnd":765,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/rcc/n6.rs#L729-L765","documentation":"During PLL frequency computation for STM32N6, embassy-stm32 matches on the selected PLL source (Pllsel). Only HSI, MSI, HSE and I2S_CKIN are valid; any other Pllsel discriminant (a reserved value, reached via from_bits on raw register/config bits) hits the wildcard arm and panics. It guards against computing frequencies from an undefined clock source.","triggerScenarios":"pll_output called with Pll::DivP (non-bypass) config whose `source` field holds a reserved Pllsel value — i.e. a Pllsel constructed from raw bits not corresponding to Hsi/Msi/Hse/I2sCkin.","commonSituations":"Casting arbitrary integers into Pllsel via from_bits/transmute; a config generated from device-tree or HAL registers containing a reserved encoding; corrupt or vendor-tool-generated clock configs.","solutions":["Set the PLL source to Pllsel::Hsi, Pllsel::Msi, Pllsel::Hse or Pllsel::I2sCkin explicitly","Ensure the input.hsi/msi/hse/i2s_ckin Option is populated in the RccInput for the chosen source (unwrap! would otherwise panic too)","Avoid constructing Pllsel from raw bits; use the enum variants"],"exampleFix":"// before\nlet pll = Pll::DivP { source: unsafe { Pllsel::from_bits(0x7) }, divm, divn, divp1, divp2 };\n// after\nlet pll = Pll::DivP { source: Pllsel::Hse, divm, divn, divp1, divp2 };","handlingStrategy":"validation","validationCode":"fn pll_source_is_real(s: Pllsel) -> bool {\n    matches!(s, Pllsel::Hsi | Pllsel::Msi | Pllsel::Hse | Pllsel::I2sCkin)\n}\nassert!(pll_source_is_real(my_pll.source));","typeGuard":"fn as_valid_pll_source(bits: u8) -> Option<Pllsel> {\n    Pllsel::from_bits(bits).filter(|s| !matches!(s, Pllsel::_RESERVED_5 | Pllsel::_RESERVED_6 | Pllsel::_RESERVED_7))\n}","tryCatchPattern":null,"preventionTips":["Never build Pllsel from raw integers; use enum variants","Only enable the PLL source variants your chip/package supports","Validate generated/HAL-converted clock configs against the enum before init"],"tags":["rust","embedded","rcc","pll","stm32n6"],"backgroundTag":"unsupported-enum-value","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}