{"record":{"id":"20a873b7dc594027","repo":"wasmerio/wasmer","slug":"not-yet-implemented-20a873","errorCode":null,"errorMessage":"not yet implemented","messagePattern":"not yet implemented","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"critical","filePath":"lib/compiler-singlepass/src/machine_riscv.rs","lineNumber":2853,"sourceCode":"        self.assembler.emit_pop(size, loc)\n    }\n\n    fn emit_relaxed_mov(\n        &mut self,\n        sz: Size,\n        src: Location,\n        dst: Location,\n    ) -> Result<(), CompileError> {\n        self.emit_relaxed_binop(Assembler::emit_mov, sz, src, dst)\n    }\n\n    fn emit_relaxed_cmp(\n        &mut self,\n        _sz: Size,\n        _src: Location,\n        _dst: Location,\n    ) -> Result<(), CompileError> {\n        todo!();\n    }\n\n    fn emit_memory_fence(&mut self) -> Result<(), CompileError> {\n        self.assembler.emit_rwfence()\n    }\n\n    fn emit_relaxed_sign_extension(\n        &mut self,\n        sz_src: Size,\n        src: Location,\n        sz_dst: Size,\n        dst: Location,\n    ) -> Result<(), CompileError> {\n        let mut temps = vec![];\n\n        match (src, dst) {\n            (Location::Memory(reg, offset), Location::GPR(_)) => {\n                let src = if ImmType::Bits12.compatible_imm(offset as _) {","sourceCodeStart":2835,"sourceCodeEnd":2871,"githubUrl":"https://github.com/wasmerio/wasmer/blob/8c4b9ee9d33fb2068863fbb3d328683e7e6ff7f5/lib/compiler-singlepass/src/machine_riscv.rs#L2835-L2871","documentation":"emit_relaxed_cmp for the RISC-V singlepass backend is a stub: it is declared to emit a relaxed-width comparison but the body is `todo!()`, so any code path that lowers a comparison through it panics with 'not yet implemented'. The RISC-V port has not implemented this instruction-lowering hook.","triggerScenarios":"Any singlepass-on-riscv64 compilation whose instruction selection reaches emit_relaxed_cmp (integer comparisons emitted in relaxed form), e.g. wasm i32/i64 comparison ops (eq/ne/lt/gt/le/ge) routed to this backend.","commonSituations":"Using wasmer's experimental RISC-V singlepass backend on any nontrivial wasm module — nearly every module contains comparisons — so this fires almost immediately on riscv hosts with singlepass selected.","solutions":["Select the cranelift compiler for riscv64 targets instead of singlepass","Upgrade wasmer to a release where emit_relaxed_cmp is implemented for RISC-V","Backend contributors: implement the hook by emitting a slt/xor-based comparison of the requested Size","Avoid singlepass on RISC-V until the port is marked complete upstream"],"exampleFix":"// before (machine_riscv.rs)\nfn emit_relaxed_cmp(&mut self, _sz: Size, _src: Location, _dst: Location) -> Result<(), CompileError> {\n    todo!();\n}\n// after\nfn emit_relaxed_cmp(&mut self, sz: Size, src: Location, dst: Location) -> Result<(), CompileError> {\n    self.emit_cmp(sz, src, dst) // or a proper sltu/xori sequence\n}","handlingStrategy":"fallback","validationCode":"// refuse singlepass on riscv until emit_relaxed_cmp exists\nif is_riscv_target() && uses_singlepass() { return Err(\"singlepass unsupported on riscv; use cranelift\"); }","typeGuard":"fn compiler_supports_target(cfg: &dyn CompilerConfig, triple: &Triple) -> bool {\n    !(triple.architecture == Architecture::Riscv64 && cfg.name() == \"singlepass\")\n}","tryCatchPattern":null,"preventionTips":["Use cranelift as the compiler for any riscv64 deployment","Never enable experimental singlepass-on-riscv in production configs","Before upgrading, diff machine_riscv.rs for remaining todo!() stubs","Add CI on riscv targets running representative wasm workloads"],"tags":["riscv","singlepass","unimplemented","wasm"],"backgroundTag":"singlepass-riscv-unimplemented","analyzedSha":"8c4b9ee9d33fb2068863fbb3d328683e7e6ff7f5","analyzedAt":"2026-09-01T23:06:31.009Z","contentChangedAt":null,"schemaVersion":2},"datasetVersion":"2026-09-09T06:17:21.866Z"}