{"record":{"id":"267978dfffb86c53","repo":"embassy-rs/embassy","slug":"msi-is-not-ready-to-be-selected-as-system-clock-so","errorCode":null,"errorMessage":"MSI is not ready to be selected as system clock source","messagePattern":"MSI is not ready to be selected as system clock source","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/rcc/n6.rs","lineNumber":371,"sourceCode":"    debug!(\"configuring cpuclk\");\n    match config.cpu {\n        CpuClk::Hsi if !RCC.sr().read().hsirdy() => panic!(\"HSI is not ready to be selected as CPU clock source\"),\n        CpuClk::Msi if !RCC.sr().read().msirdy() => panic!(\"MSI is not ready to be selected as CPU clock source\"),\n        CpuClk::Hse if !RCC.sr().read().hserdy() => panic!(\"HSE is not ready to be selected as CPU clock source\"),\n        CpuClk::Ic1 if !ic_enabled(1) => panic!(\"IC1 is not ready to be selected as CPU clock source\"),\n        _ => {}\n    }\n    // set source\n    let cpusw = Cpusw::from_bits(config.cpu.to_bits());\n    RCC.cfgr().modify(|w| w.set_cpusw(cpusw));\n    // wait for changes to take effect\n    while RCC.cfgr().read().cpusws() != Cpusws::from_bits(config.cpu.to_bits()) {}\n\n    // sysclk\n    debug!(\"configuring sysclk\");\n    match config.sys {\n        SysClk::Hsi if !RCC.sr().read().hsirdy() => panic!(\"HSI is not ready to be selected as system clock source\"),\n        SysClk::Msi if !RCC.sr().read().msirdy() => panic!(\"MSI is not ready to be selected as system clock source\"),\n        SysClk::Hse if !RCC.sr().read().hserdy() => panic!(\"HSE is not ready to be selected as system clock source\"),\n        SysClk::Ic2 if !ic_enabled(2) || !ic_enabled(6) || !ic_enabled(11) => panic!(\n            \"IC2 is not ready to be selected as system clock source (make sure that IC6 and IC11 were configured as well)\"\n        ),\n        _ => {}\n    }\n    // switch the system bus clock\n    let syssw = Syssw::from_bits(config.sys.to_bits());\n    RCC.cfgr().modify(|w| w.set_syssw(syssw));\n    // wait for changes to be applied\n    while RCC.cfgr().read().syssws() != Syssws::from_bits(config.sys.to_bits()) {}\n\n    // decreasing dividers\n    debug!(\"configuring decreasing pclk dividers\");\n    RCC.cfgr2().modify(|w| {\n        if config.ahb < w.hpre() {\n            debug!(\"  - AHB\");\n            w.set_hpre(config.ahb);","sourceCodeStart":353,"sourceCodeEnd":389,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/rcc/n6.rs#L353-L389","documentation":"On STM32N6, before switching the system clock to MSI, the code checks `RCC.sr().msirdy()`. If MSI is not running and ready, selecting it as the system bus clock source is invalid and the library panics.","triggerScenarios":"Setting `config.sys = SysClk::Msi` while `msirdy()` is false — MSI not configured/enabled, or MSI disabled earlier in the init sequence before the sysclk switch.","commonSituations":"Choosing MSI as sysclk without an msi config entry; mixed cpu/sys configs where one stage turns MSI off; low-power configs relying on MSI but not enabling it.","solutions":["Add an MSI config (`msi: Some(MsiConfig...)`) to the rcc config so MSI is enabled and ready.","Or pick a ready sysclk source (Hsi/Hse/Ic2) in `config.sys`.","Ensure neither the cpu-clock stage nor other code disables MSI before the sysclk switch."],"exampleFix":"// before\nrcc: RccConfig { sys: SysClk::Msi, ..Default::default() }, // msi absent\n// after\nrcc: RccConfig { msi: Some(MsiConfig::default()), sys: SysClk::Msi, ..Default::default() },","handlingStrategy":"validation","validationCode":"if config.rcc.sys == SysClk::Msi && config.rcc.msi.is_none() {\n    panic!(\"SysClk::Msi requires an msi config in rcc\");\n}","typeGuard":"fn msi_ready_for_sys(rcc: &RccConfig) -> bool {\n    rcc.sys != SysClk::Msi || rcc.msi.is_some()\n}","tryCatchPattern":null,"preventionTips":["Pair SysClk::Msi with an explicit MsiConfig entry.","Ensure earlier init stages (cpu switch) leave MSI enabled.","Test init on the actual board so msirdy timing issues surface early."],"tags":["rust","embedded","rcc","stm32n6","msi","sysclk","panic"],"backgroundTag":"invalid-state-transition","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}