{"record":{"id":"3120441505a61d95","repo":"embassy-rs/embassy","slug":"maximal-allowed-frequency-for-the-adc-is-mhz-an-312044","errorCode":null,"errorMessage":"Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.","messagePattern":"Maximal allowed frequency for the ADC is (.+?) MHz and it varies with different packages, refer to ST docs for more information\\.","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/adc/v4.rs","lineNumber":338,"sourceCode":"    /// Create a new ADC driver.\n    pub fn new(adc: Peri<'d, T>) -> Self {\n        rcc::enable_and_reset::<T>();\n\n        #[cfg(not(any(stm32u3, stm32n6, stm32c5)))]\n        let prescaler = from_ker_ck(T::frequency());\n        #[cfg(not(any(stm32u3, stm32n6, stm32c5)))]\n        T::common_regs().ccr().modify(|w| w.set_presc(prescaler));\n        #[cfg(not(any(stm32u3, stm32n6, stm32c5)))]\n        let frequency = T::frequency() / prescaler;\n\n        #[cfg(any(stm32u3, stm32n6, stm32c5))]\n        let frequency = T::frequency();\n\n        info!(\"ADC frequency set to {}\", frequency);\n\n        #[cfg(not(stm32c5))] // C5 checks this in its rcc\n        if frequency > MAX_ADC_CLK_FREQ {\n            panic!(\n                \"Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.\",\n                MAX_ADC_CLK_FREQ.0 / 1_000_000\n            );\n        }\n\n        #[cfg(stm32h7)]\n        {\n            let boost = if frequency < Hertz::khz(6_250) {\n                Boost::Lt625\n            } else if frequency < Hertz::khz(12_500) {\n                Boost::Lt125\n            } else if frequency < Hertz::mhz(25) {\n                Boost::Lt25\n            } else {\n                Boost::Lt50\n            };\n            T::regs().cr().modify(|w| w.set_boost(boost));\n        }","sourceCodeStart":320,"sourceCodeEnd":356,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/adc/v4.rs#L320-L356","documentation":"The v4 ADC driver (C0/G4/H7-class per stm32u5/h7 etc.) checks the ADC kernel clock against MAX_ADC_CLK_FREQ after construction and panics if it exceeds the limit, since datasheet limits guarantee conversion accuracy. On STM32C5 the RCC layer already performs this check, so the check is cfg'd out there. The limit varies by package/voltage per ST docs.","triggerScenarios":"Calling `Adc::new(...)` when T::frequency() (the ADC kernel clock from RCC) is greater than MAX_ADC_CLK_FREQ, on any supported chip except STM32C5.","commonSituations":"Mapping the ADC kernel clock from a fast AHB/PLL output without prescaling; overclocked RCC configs; reusing clock init from a different board; bumping embassy-stm32 and encountering stricter runtime checks.","solutions":["Select a slower ADC kernel clock source (e.g. divided HCLK, HSI16, or per-family ADC prescaler) in the RCC config","Lower the source frequency feeding the ADC (reduce PLL/SYSCLK)","Consult the ST datasheet for the exact limit for your package/voltage and recompute the prescaler"],"exampleFix":"// before\nconfig.rcc.adc_clock_source = AdcClockSource::AHB; // too fast\n// after\nconfig.rcc.adc_clock_source = AdcClockSource::HSI16; // or AHB with prescaler, <= MAX_ADC_CLK_FREQ","handlingStrategy":"validation","validationCode":"let adc_clk_hz = adc_kernel_clock_hz();\nassert!(adc_clk_hz <= MAX_ADC_CLK_FREQ_HZ, \"ADC kernel clock {} Hz exceeds limit\", adc_clk_hz);","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Choose a divided or low-speed ADC kernel clock source in RCC config","Recalculate ADC clock after any PLL/SYSCLK change","Check per-package limits in the ST datasheet (they vary with voltage)","Print the ADC frequency at startup during bring-up"],"tags":["embedded","stm32","adc","clock-config","rust"],"backgroundTag":"value-out-of-range","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}