{"record":{"id":"3866620769f383a0","repo":"embassy-rs/embassy","slug":"if-pll-source-is-hsi-pll-prediv-must-be-2","errorCode":null,"errorMessage":"if PLL source is HSI, PLL prediv must be 2.","messagePattern":"if PLL source is HSI, PLL prediv must be 2\\.","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/rcc/f013.rs","lineNumber":254,"sourceCode":"        }\n\n        // Configure PLL3\n        if let Some(pll3) = config.pll3 {\n            RCC.cfgr2().modify(|w| w.set_pll3mul(pll3.mul));\n            RCC.cr().modify(|w| w.set_pll3on(true));\n            while !RCC.cr().read().pll3rdy() {}\n        }\n    }\n\n    // Enable PLL\n    let pll = config.pll.map(|pll| {\n        let (src_val, src_freq) = match pll.src {\n            #[cfg(any(rcc_f0v3, rcc_f0v4, rcc_f3v3))]\n            PllSource::HSI => (Pllsrc::HsiDivPrediv, unwrap!(hsi)),\n            #[cfg(not(any(rcc_f0v3, rcc_f0v4, rcc_f3v3)))]\n            PllSource::HSI => {\n                if pll.prediv != PllPreDiv::Div2 {\n                    panic!(\"if PLL source is HSI, PLL prediv must be 2.\");\n                }\n                (Pllsrc::HsiDiv2, unwrap!(hsi))\n            }\n            PllSource::HSE => {\n                #[cfg(any(stm32f105, stm32f107))]\n                RCC.cfgr2().modify(|w| w.set_prediv1src(Prediv1src::Hse));\n\n                (Pllsrc::HseDivPrediv, unwrap!(hse))\n            }\n            #[cfg(rcc_f0v4)]\n            PllSource::HSI48 => (Pllsrc::Hsi48DivPrediv, unwrap!(hsi48)),\n            #[cfg(any(stm32f105, stm32f107))]\n            PllSource::PLL2 => {\n                if config.pll2.is_none() {\n                    panic!(\"if PLL source is PLL2, Config::pll2 must also be set.\");\n                }\n                RCC.cfgr2().modify(|w| w.set_prediv1src(Prediv1src::Pll2));\n","sourceCodeStart":236,"sourceCodeEnd":272,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/rcc/f013.rs#L236-L272","documentation":"On certain STM32 F0/F1/F3 parts (not rcc_f0v3/f0v4/f3v3 silicon), the RCC hardware hardwires the HSI path into the PLL to a fixed divide-by-2, so the configurable prediv is ignored. embassy-stm32 panics at init if you specify PllSource::HSI with a PllPreDiv other than Div2, since the requested prediv cannot actually be applied.","triggerScenarios":"Calling embassy_stm32::rcc init with Config containing pll configured as PllSource::HSI and prediv set to Div1, Div3, Div4, etc., on a target where cfg(not(any(rcc_f0v3, rcc_f0v4, rcc_f3v3))) applies.","commonSituations":"Porting an RCC config from an F0 v3 or F3 v3 board to a different F0/F3 chip that hardwires HSI/2; copying PLL setups between chip families; assuming prediv is a general-purpose knob on HSI source.","solutions":["Set pll.prediv to PllPreDiv::Div2 when using PllSource::HSI on these parts.","If you need a different prediv, switch the PLL source to HSE, which honors the configurable prediv.","Adjust the pll.mul value to compensate so the target PLL output frequency is still achieved with /2."],"exampleFix":"// before\nlet config = Config {\n    pll: Some(Pll { source: PllSource::HSI, prediv: PllPreDiv::Div1, mul: Mul::Mul6 }),\n    ..Default::default()\n};\n// after\nlet config = Config {\n    pll: Some(Pll { source: PllSource::HSI, prediv: PllPreDiv::Div2, mul: Mul::Mul12 }),\n    ..Default::default()\n};","handlingStrategy":"validation","validationCode":"if pll.source == PllSource::HSI {\n    assert!(pll.prediv == PllPreDiv::Div2, \"HSI PLL source requires prediv = Div2 on this chip\");\n}","typeGuard":null,"tryCatchPattern":null,"preventionTips":["HSI is hardwired to /2 on most F0/F1/F3 (except F0v3/F0v4/F3v3).","Compensate frequency changes via pll.mul, not prediv, when using HSI.","Check the cfg feature gates for your exact chip before reusing PLL configs across boards."],"tags":["rust","embedded","rcc","pll","stm32"],"backgroundTag":"invalid-config-value","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}