{"record":{"id":"3d1f64668f47455f","repo":"embassy-rs/embassy","slug":"hclk-results-in-mdc-clock-2-5mhz-even-for-the-hi","errorCode":null,"errorMessage":"HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider","messagePattern":"HCLK results in MDC clock > 2\\.5MHz even for the highest CSR clock divider","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/eth/sma/v1.rs","lineNumber":53,"sourceCode":"            reg.modify(|w| {\n                w.set_ethen(true);\n            })\n        });\n\n        let hclk = unsafe { crate::rcc::get_freqs().hclk1.to_hertz() };\n        let hclk = unwrap!(hclk, \"SMA requires HCLK to be enabled, but it was not.\");\n        let hclk_mhz = hclk.0 / 1_000_000;\n\n        // Set the MDC clock frequency in the range 1MHz - 2.5MHz\n        let clock_range = match hclk_mhz {\n            0..=24 => panic!(\"Invalid HCLK frequency - should be at least 25 MHz.\"),\n            25..=34 => Cr::Cr2035,     // Divide by 16\n            35..=59 => Cr::Cr3560,     // Divide by 26\n            60..=99 => Cr::Cr60100,    // Divide by 42\n            100..=149 => Cr::Cr100150, // Divide by 62\n            150..=216 => Cr::Cr150168, // Divide by 102\n            _ => {\n                panic!(\"HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider\")\n            }\n        };\n\n        Self {\n            _peri: peri,\n            clock_range,\n            _pins: [\n                new_pin!(mdio, AfType::output(OutputType::PushPull, Speed::VeryHigh)).unwrap(),\n                new_pin!(mdc, AfType::output(OutputType::PushPull, Speed::VeryHigh)).unwrap(),\n            ],\n        }\n    }\n}\n\nimpl<T: Instance> StationManagement for Sma<'_, T> {\n    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {\n        let (macmiiar, macmiidr) = T::regs();\n","sourceCodeStart":35,"sourceCodeEnd":71,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/eth/sma/v1.rs#L35-L71","documentation":"The ETH_MAC needs an MDC management clock in the 1-2.5 MHz window, derived from HCLK via a fixed table of CSR dividers. The match on hclk_mhz fell into the panic arm, meaning even the largest divider (divide by 124, for ~250 MHz HCLK) leaves MDC above 2.5 MHz — the input HCLK is above what the divider table supports (or below the 25 MHz minimum).","triggerScenarios":"Creating StationManagement on an eth v1 part with hclk_mhz > 216 (catch-all match arm).","commonSituations":"Overclocked HCLK1 on F4/F7 v1 parts; reusing H5-style high-frequency RCC configs on v1 boards.","solutions":["Lower HCLK1 to <= 216 MHz (150..=216 arm) in the RCC config.","Add a divider so the ETH kernel clock (hclk1) is in range.","Use a v2 MAC/chip whose CSR clock range supports higher HCLK."],"exampleFix":"// before\nconfig.pll = Pll { freq: 240.MHz(), .. };\n// after\nconfig.pll = Pll { freq: 216.MHz(), .. }; // Cr150168","handlingStrategy":"validation","validationCode":"let hclk_mhz = embassy_stm32::rcc::get_freqs().hclk1.0 / 1_000_000;\nassert!(hclk_mhz <= 216, \"v1 Ethernet requires HCLK1 <= 216 MHz, got {} MHz\", hclk_mhz);","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Cap HCLK1 at 216 MHz on v1 Ethernet parts.","Do not reuse high-frequency (H5-style) RCC configs on v1 boards."],"tags":["embedded","rust","ethernet","clock-config","stm32"],"backgroundTag":"value-out-of-range","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}