{"record":{"id":"3e79593f69ad75c6","repo":"embassy-rs/embassy","slug":"maximal-allowed-frequency-for-the-adc-is-mhz-an","errorCode":null,"errorMessage":"Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.","messagePattern":"Maximal allowed frequency for the ADC is (.+?) MHz and it varies with different packages, refer to ST docs for more information\\.","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/adc/c0.rs","lineNumber":199,"sourceCode":"        self.isr().read().eoc()\n    }\n}\n\nimpl<'d, T: Instance<Regs = crate::pac::adc::Adc>> Adc<'d, T> {\n    /// Create a new ADC driver.\n    pub fn new(adc: Peri<'d, T>, resolution: Resolution) -> Self {\n        rcc::enable_and_reset::<T>();\n\n        T::regs().cfgr2().modify(|w| w.set_ckmode(Ckmode::Sysclk));\n\n        let prescaler = from_ker_ck(T::frequency());\n        T::common_regs().ccr().modify(|w| w.set_presc(prescaler));\n\n        let frequency = T::frequency() / prescaler;\n        debug!(\"ADC frequency set to {}\", frequency);\n\n        if frequency > MAX_ADC_CLK_FREQ {\n            panic!(\n                \"Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.\",\n                MAX_ADC_CLK_FREQ.0 / 1_000_000\n            );\n        }\n\n        T::regs().cr().modify(|reg| {\n            reg.set_advregen(true);\n        });\n\n        // \"The software must wait for the ADC voltage regulator startup time.\"\n        // See datasheet for the value.\n        block_for_us(TIME_ADC_VOLTAGE_REGUALTOR_STARTUP_US as u64 + 1);\n\n        T::regs().cfgr1().modify(|reg| reg.set_res(resolution));\n\n        // We have to make sure AUTOFF is OFF, but keep its value after calibration.\n        let autoff_value = T::regs().cfgr1().read().autoff();\n        T::regs().cfgr1().modify(|w| w.set_autoff(false));","sourceCodeStart":181,"sourceCodeEnd":217,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/adc/c0.rs#L181-L217","documentation":"The C0-series ADC driver applies a prescaler on the ADC common clock (CCR.PRESC) and picks the largest one it supports. If the ADC clock frequency still exceeds MAX_ADC_CLK_FREQ, the constructor panics, because exceeding the ADC clock limit violates ST's electrical specification and corrupts conversion accuracy. The limit varies per package/voltage, so ST's docs are referenced.","triggerScenarios":"Calling `Adc::new(...)` for an STM32C0 target when T::frequency() (the ADC kernel clock) divided by the maximum prescaler still exceeds MAX_ADC_CLK_FREQ.","commonSituations":"High system clock (e.g. 48 MHz HSI at max PLL) feeding the ADC with no slow kernel-clock source selected; reusing RCC config from another board; upgrading embassy-stm32 and hitting stricter frequency checks.","solutions":["Set the ADC kernel clock source in RCC config to a slower clock (e.g. PCLK/HSI16 with proper division)","Lower SYSCLK so the derived ADC clock is within the datasheet limit","Verify the exact MAX_ADC_CLK_FREQ for your package in the ST datasheet and adjust clocking accordingly"],"exampleFix":"// before\nlet config = Config::default(); // ADC clock too fast\n// after\nconfig.rcc.adc_clock_source = AdcClockSource::SysClkDiv...; // choose a divided source so adc_clk <= MAX_ADC_CLK_FREQ","handlingStrategy":"validation","validationCode":"let adc_clk_hz = adc_kernel_clock_hz(); // from RCC config\nassert!(adc_clk_hz <= MAX_ADC_CLK_FREQ_HZ, \"ADC clock {} Hz exceeds limit\", adc_clk_hz);","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Design the clock tree with the ADC limit in mind from the start","Use a dedicated slow kernel-clock source for the ADC","Verify limits in the C0 datasheet for your package and voltage","Log ADC frequency at startup during bring-up"],"tags":["embedded","stm32","adc","clock-config","rust"],"backgroundTag":"value-out-of-range","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}