{"record":{"id":"3ff35cdac5d99a52","repo":"embassy-rs/embassy","slug":"dts-pclk-frequency-must-be-less-than-127-mhz","errorCode":null,"errorMessage":"DTS PCLK frequency must be less than 127 MHz.","messagePattern":"DTS PCLK frequency must be less than 127 MHz\\.","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/dts/mod.rs","lineNumber":92,"sourceCode":"pub struct Dts<'d> {\n    _peri: Peri<'d, DTS>,\n}\n\nstatic WAKER: AtomicWaker = AtomicWaker::new();\n\nimpl<'d> Dts<'d> {\n    /// Create a new temperature sensor driver.\n    pub fn new(\n        _peri: Peri<'d, DTS>,\n        _irq: impl interrupt::typelevel::Binding<interrupt::typelevel::DTS, InterruptHandler> + 'd,\n        config: Config,\n    ) -> Self {\n        rcc::enable_and_reset::<DTS>();\n\n        let prescaler = rcc::frequency::<DTS>() / MAX_DTS_CLK_FREQ;\n\n        if prescaler > 127 {\n            panic!(\"DTS PCLK frequency must be less than 127 MHz.\");\n        }\n\n        Self::regs().cfgr1().modify(|w| {\n            w.set_refclk_sel(false);\n            w.set_hsref_clk_div(prescaler as u8);\n            w.set_q_meas_opt(false);\n            // Software trigger\n            w.set_intrig_sel(0);\n            w.set_smp_time(config.sample_time as u8);\n            w.set_intrig_sel(config.trigger as u8);\n            w.set_start(true);\n            w.set_en(true);\n        });\n\n        interrupt::DTS.unpend();\n        unsafe { interrupt::DTS.enable() };\n\n        Self { _peri }","sourceCodeStart":74,"sourceCodeEnd":110,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/dts/mod.rs#L74-L110","documentation":"The DTS (digital temperature sensor) kernel clock must be slow enough that (freq / MAX_DTS_CLK_FREQ) fits in the 7-bit HSREF_CLK_DIV field (max 127). If the computed prescaler exceeds 127 the divider cannot be represented in the register and the driver panics.","triggerScenarios":"Calling Dts::new() while the RCC-configured DTS/PCLK frequency makes prescaler = freq / MAX_DTS_CLK_FREQ > 127.","commonSituations":"High system/PCLK frequencies (250 MHz+) without a dedicated DTS kernel-clock divider; default RCC setups on H5/U5 boards.","solutions":["Lower the DTS kernel clock in the RCC config so freq / MAX_DTS_CLK_FREQ <= 127.","Add a divider or lower PCLK/system frequency for the DTS peripheral.","Check rcc::frequency::<DTS>() before constructing the sensor."],"exampleFix":"// before\ncfg.dts_clock = None; // inherits fast PCLK\n// after\ncfg.dts_clock = Some(Hz(50_000_000)); // prescaler <= 127","handlingStrategy":"validation","validationCode":"let dts_hz = embassy_stm32::rcc::frequency::<DTS>().0;\nassert!(dts_hz / MAX_DTS_CLK_FREQ <= 127, \"DTS kernel clock too high: {} Hz\", dts_hz);","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Configure a DTS kernel-clock prescaler so freq / MAX_DTS_CLK_FREQ <= 127.","Log rcc::frequency::<DTS>() during bring-up on high-frequency boards."],"tags":["embedded","rust","stm32","clock-config","dts"],"backgroundTag":"value-out-of-range","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}