{"record":{"id":"415c115356903ec1","repo":"embassy-rs/embassy","slug":"ic-source-was-set-to-pll-but-it-is-not-curren","errorCode":null,"errorMessage":"IC{} source was set to PLL{}, but it is not currently enabled","messagePattern":"IC(.+?) source was set to PLL(.+?), but it is not currently enabled","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/rcc/n6.rs","lineNumber":314,"sourceCode":"        config.ic12,\n        config.ic13,\n        config.ic14,\n        config.ic15,\n        config.ic16,\n        config.ic17,\n        config.ic18,\n        config.ic19,\n        config.ic20,\n    ]\n    .iter()\n    .enumerate()\n    {\n        // Skip disabled ICs\n        let Some(ic) = ic else { continue };\n\n        let ic_source = ic.source.to_bits();\n        if !pll_source_ready(ic_source) {\n            panic!(\n                \"IC{} source was set to PLL{}, but it is not currently enabled\",\n                index + 1,\n                ic_source\n            )\n        }\n\n        RCC.iccfgr(index).write(|w| {\n            w.set_icsel(ic.source);\n            w.set_icint(ic.divider);\n        });\n        RCC.divensr().modify(|w| w.0 = 1 << index);\n    }\n\n    // handle increasing dividers\n    debug!(\"configuring increasing pclk dividers\");\n    RCC.cfgr2().modify(|w| {\n        if config.apb1 > w.ppre1() {\n            debug!(\"  - APB1\");","sourceCodeStart":296,"sourceCodeEnd":332,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/rcc/n6.rs#L296-L332","documentation":"On STM32N6, an output-clock (ICx) divider was configured with a source whose `pll_source_ready` check fails, meaning the referenced PLL (or PLLx input) is not enabled. embassy-stm32 panics rather than silently producing a wrong frequency, since the IC output would be invalid.","triggerScenarios":"Setting `config.ics[?] = Ic { source: IcSource::Pll1/Pll2/Pll3... , ... }` for a PLL that was not enabled in the same init (its `pll` entry absent/None, or the PLL output feeding the IC not configured).","commonSituations":"Configuring an ICx routed to PLL2 or PLL3 while only PLL1 is set up; copy-pasting IC configs between boards; partial PLL config after refactoring so a PLL referenced by ICs is dropped.","solutions":["Enable the PLL that the IC source references: add its `PllConfig` (with valid source) to the rcc config.","Or change the ICx `source` to a currently-enabled PLL/oscillator.","If the IC is unused, set that IC entry to None so it is skipped."],"exampleFix":"// before\nics: [Some(Ic { source: IcSource::Pll2, ..Default::default() }), ..],\n// with no pll2 configured\n// after\n// either configure pll2:\npll2: Some(PllConfig { source: PllSource::Hse, ..Default::default() }),\n// or drop the IC:\nics: [None, ..],","handlingStrategy":"validation","validationCode":"for ic in &config.rcc.ics {\n    if let Some(ic) = ic {\n        assert!(matches!(ic.source, IcSource::Pll1 if config.rcc.pll1.is_some()), \"IC source PLL must be enabled\");\n    }\n}","typeGuard":"fn ic_source_ready(ic: &Ic, rcc: &RccConfig) -> bool {\n    match ic.source {\n        IcSource::Pll1 => rcc.pll1.is_some(),\n        IcSource::Pll2 => rcc.pll2.is_some(),\n        IcSource::Pll3 => rcc.pll3.is_some(),\n        _ => true,\n    }\n}","tryCatchPattern":null,"preventionTips":["Configure every PLL that any ICx source references before init().","Set unused IC entries to None instead of pointing them at unenabled PLLs.","When copying board configs, check ics and pll sections change together."],"tags":["rust","embedded","rcc","stm32n6","clock-config","panic"],"backgroundTag":"invalid-config-value","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}