{"record":{"id":"42420ed31f3cd8bd","repo":"embassy-rs/embassy","slug":"phy-did-not-respond","errorCode":null,"errorMessage":"PHY did not respond","messagePattern":"PHY did not respond","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/eth/generic_phy.rs","lineNumber":111,"sourceCode":"}\n\nimpl<SM: StationManagement> Phy for GenericPhy<SM> {\n    fn phy_reset(&mut self) {\n        // Detect SMI address\n        if self.phy_addr == 0xFF {\n            for addr in 0..32 {\n                self.sm.smi_write(addr, PHY_REG_BCR, PHY_REG_BCR_RESET);\n                for _ in 0..10 {\n                    if self.sm.smi_read(addr, PHY_REG_BCR) & PHY_REG_BCR_RESET != PHY_REG_BCR_RESET {\n                        trace!(\"Found ETH PHY on address {}\", addr);\n                        self.phy_addr = addr;\n                        return;\n                    }\n                    // Give PHY a total of 100ms to respond\n                    block_for_us(10000);\n                }\n            }\n            panic!(\"PHY did not respond\");\n        }\n\n        self.sm.smi_write(self.phy_addr, PHY_REG_BCR, PHY_REG_BCR_RESET);\n        while self.sm.smi_read(self.phy_addr, PHY_REG_BCR) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}\n    }\n\n    fn phy_init(&mut self) {\n        // Clear WU CSR\n        self.smi_write_ext(PHY_REG_WUCSR, 0);\n\n        #[cfg(eth_v2a)]\n        {\n            // The v2a MAC is fixed at 100M full duplex; advertise only that.\n            let antx = self.sm.smi_read(self.phy_addr, PHY_REG_ANTX);\n            let antx = (antx & !PHY_REG_ANTX_TECH) | PHY_REG_ANTX_100BTX_FD;\n            self.sm.smi_write(self.phy_addr, PHY_REG_ANTX, antx);\n            self.sm.smi_write(self.phy_addr, PHY_REG_GBCR, 0);\n        }","sourceCodeStart":93,"sourceCodeEnd":129,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/eth/generic_phy.rs#L93-L129","documentation":"After issuing an SMI read, the driver waits up to 100 ms for the PHY to respond; if no answer appears it panics. This means the Ethernet PHY is not answering MDIO transactions at the given PHY address.","triggerScenarios":"Ethinic/generic PHY init calling phy_reset() when no PHY acknowledges on MDIO within 100 ms — wrong phy address, missing/powered-down PHY, or MDIO/MDC wiring issue.","commonSituations":"Custom boards where the PHY strap address differs from the assumed default; missing 25 MHz PHY crystal or RMII 50 MHz ref clock; MDC/MDIO pins misconfigured.","solutions":["Verify the PHY address from strap pins/schematic and pass the correct value to the PHY constructor.","Check PHY power, reset line, and reference clock at board level.","Confirm MDC/MDIO pin configuration in the embassy-stm32 pins! macro.","Probe the MDIO bus with a logic analyzer; fix/replace silent PHY hardware."],"exampleFix":"// before\nlet phy = EmbassyEthernetPhy::new(dev, 0); // assumed addr 0\n// after\nlet phy = EmbassyEthernetPhy::new(dev, 1); // actual address from strap pins","handlingStrategy":"validation","validationCode":"let phy_addr = read_phy_addr_straps();\nassert!(phy_addr <= 31, \"invalid PHY address: {}\", phy_addr);","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Confirm PHY address from strap pins/schematic, not library defaults.","Check PHY power, reset, and reference clock at board level.","Probe MDIO/MDC with a logic analyzer if init hangs."],"tags":["embedded","rust","ethernet","phy","hardware"],"backgroundTag":"request-timeout","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}