{"record":{"id":"42f14a430386563c","repo":"embassy-rs/embassy","slug":"if-pll-source-is-pll2-config-pll2-must-also-be-s","errorCode":null,"errorMessage":"if PLL source is PLL2, Config::pll2 must also be set.","messagePattern":"if PLL source is PLL2, Config::pll2 must also be set\\.","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/rcc/f013.rs","lineNumber":269,"sourceCode":"            #[cfg(not(any(rcc_f0v3, rcc_f0v4, rcc_f3v3)))]\n            PllSource::HSI => {\n                if pll.prediv != PllPreDiv::Div2 {\n                    panic!(\"if PLL source is HSI, PLL prediv must be 2.\");\n                }\n                (Pllsrc::HsiDiv2, unwrap!(hsi))\n            }\n            PllSource::HSE => {\n                #[cfg(any(stm32f105, stm32f107))]\n                RCC.cfgr2().modify(|w| w.set_prediv1src(Prediv1src::Hse));\n\n                (Pllsrc::HseDivPrediv, unwrap!(hse))\n            }\n            #[cfg(rcc_f0v4)]\n            PllSource::HSI48 => (Pllsrc::Hsi48DivPrediv, unwrap!(hsi48)),\n            #[cfg(any(stm32f105, stm32f107))]\n            PllSource::PLL2 => {\n                if config.pll2.is_none() {\n                    panic!(\"if PLL source is PLL2, Config::pll2 must also be set.\");\n                }\n                RCC.cfgr2().modify(|w| w.set_prediv1src(Prediv1src::Pll2));\n\n                let pll2 = unwrap!(config.pll2);\n                let in_freq = hse.unwrap() / config.prediv2;\n                let pll2freq = in_freq * pll2.mul;\n\n                (Pllsrc::HseDivPrediv, pll2freq)\n            }\n        };\n        let in_freq = src_freq / pll.prediv;\n\n        rcc_assert!(max::PLL_IN.contains(&in_freq));\n        let out_freq = in_freq * pll.mul;\n        rcc_assert!(max::PLL_OUT.contains(&out_freq));\n\n        #[cfg(not(stm32f1))]\n        RCC.cfgr2().modify(|w| w.set_prediv(pll.prediv));","sourceCodeStart":251,"sourceCodeEnd":287,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/rcc/f013.rs#L251-L287","documentation":"On STM32F105/F107 (connectivity line), the PLL can be clocked from PLL2. Since the driver reads config.pll2 to compute frequencies and configure the shared registers, using PllSource::PLL2 for the main PLL without also supplying config.pll2 makes the configuration incomplete, so init panics with this message.","triggerScenarios":"Calling rcc init on stm32f105/stm32f107 with config.pll set to PllSource::PLL2 while config.pll2 is None. The panic fires before unwrap!(config.pll2) would even be attempted.","commonSituations":"Using the PLL2-prediv1 feature of the connectivity line but forgetting the pll2 field; porting configs from non-connectivity-line chips where PLL2 does not exist; misreading Config defaults that leave pll2 None.","solutions":["Add a Some(Pll { ... }) value to config.pll2 when selecting PllSource::PLL2.","Make sure pll2's config (prediv2, mul) yields a PLL2 frequency that keeps the main PLL within its input limits.","Alternatively, clock the main PLL from HSE or HSI if PLL2 is not actually needed."],"exampleFix":"// before\nlet config = Config {\n    pll: Some(Pll { source: PllSource::PLL2, prediv: PllPreDiv::Div1, mul: Mul::Mul9 }),\n    ..Default::default()\n};\n// after\nlet config = Config {\n    pll: Some(Pll { source: PllSource::PLL2, prediv: PllPreDiv::Div1, mul: Mul::Mul9 }),\n    pll2: Some(Pll { source: PllSource::HSE, prediv: PllPreDiv::Div1, mul: Mul2::Mul8 }),\n    prediv2: PllPreDiv::Div1,\n    ..Default::default()\n};","handlingStrategy":"validation","validationCode":"if config.pll.as_ref().map(|p| p.source) == Some(PllSource::PLL2) {\n    assert!(config.pll2.is_some(), \"PLL2 source requires config.pll2 to be set\");\n}","typeGuard":null,"tryCatchPattern":null,"preventionTips":["On F105/F107, always define pll2 (and prediv2) whenever the main PLL uses PllSource::PLL2.","Verify the PLL2 output keeps the main PLL input within datasheet limits.","Keep connectivity-line configs in a board-specific module to avoid reuse on other chips."],"tags":["rust","embedded","rcc","pll","stm32"],"backgroundTag":"missing-required-config-field","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}