{"record":{"id":"434eea3a270f7e74","repo":"jax-ml/jax","slug":"tmem-addr-ref-must-contain-a-single-element-got","errorCode":null,"errorMessage":"tmem_addr_ref must contain a single element, got: {addr_ref_ty}","messagePattern":"tmem_addr_ref must contain a single element, got: (.+?)","errorType":"exception","errorClass":"ValueError","httpStatus":null,"severity":"error","filePath":"jax/experimental/mosaic/gpu/tcgen05.py","lineNumber":1227,"sourceCode":"  @classmethod\n  def from_alloc(\n      cls,\n      tmem_addr_ref: ir.Value,\n      shape: tuple[int, int],\n      dtype,\n      collective: bool | None = None,\n      layout: TMEMLayout | None = None,\n  ) -> TMEMRef:\n    i32 = ir.IntegerType.get_signless(32)\n    if not isinstance(tmem_addr_ref.type, ir.MemRefType):\n      raise ValueError(f\"tmem_addr_ref must be a memref or a pointer, got: {tmem_addr_ref.type}\")\n    addr_ref_ty = ir.MemRefType(tmem_addr_ref.type)\n    if not utils.is_smem_ref(addr_ref_ty):\n      raise ValueError(f\"tmem_addr_ref must be in shared memory, got: {addr_ref_ty}\")\n    if addr_ref_ty.element_type != i32:\n      raise ValueError(f\"tmem_addr_ref must be an i32 memref, got: {addr_ref_ty}\")\n    if math.prod(addr_ref_ty.shape) != 1:\n      raise ValueError(f\"tmem_addr_ref must contain a single element, got: {addr_ref_ty}\")\n    i0 = arith.ConstantOp.create_index(0)\n    tmem_addr = memref.load(tmem_addr_ref, [i0] * addr_ref_ty.rank)\n    if shape[0] < 32:\n      raise ValueError(f\"TMEM refs must have at least 32 rows, got: {shape[0]}\")\n    if layout is None:\n      if collective is None:\n        raise ValueError(\n            \"collective argument must be provided when TMEM layout is inferred\"\n        )\n      layout = _infer_tmem_layout(shape, collective, packing=1)\n    # TODO: Do we have to do this??\n    # warp_idx = utils.warp_idx(sync=False)\n    # tmem_addr = arith.ori(tmem_addr, arith.shli(warp_idx, utils.c(21, i32)))\n    return cls(tmem_addr, shape, dtype, layout)\n\n  def slice(self, *idxs) -> TMEMRef:\n    i32 = ir.IntegerType.get_signless(32)\n    base_idx, slice_shape, is_squeezed = utils.parse_indices(idxs, self.shape)","sourceCodeStart":1209,"sourceCodeEnd":1245,"githubUrl":"https://github.com/jax-ml/jax/blob/1e1c6a8fc06dfcd1247076ec5cae4640cea5d7bb/jax/experimental/mosaic/gpu/tcgen05.py#L1209-L1245","documentation":"The TMEM base address occupies exactly one i32 word in shared memory; from_alloc requires math.prod(addr_ref_ty.shape) == 1 (a scalar/0-d memref, possibly with singleton dims). Multi-element memrefs are rejected because there is no defined way to pick the address among them.","triggerScenarios":"Passing a 1D memref like memref<4xi32> or memref<1x1xi32> with shape (1,1) is fine but memref<2xi32> is not; passing an array of alloc results.","commonSituations":"Allocating the address slot as a vector to 'be safe'; batching several allocations into one buffer and passing the whole buffer.","solutions":["Use a 0-d/scalar smem i32 memref for each allocation's address","Index the array memref first and pass a single-element subview (shape must reduce to product 1)","Allocate one address slot per tmem.alloc call"],"exampleFix":"# before\naddr_ref = smem_alloca(i32, [4])  # memref<4xi32>\n# after\naddr_ref = smem_alloca(i32, [])  # single-element 0-d memref","handlingStrategy":"validation","validationCode":"import math\nassert math.prod(ir.MemRefType(tmem_addr_ref.type).shape) == 1","typeGuard":"def single_element_memref(ref) -> bool:\n    t = getattr(ref, 'type', None)\n    return isinstance(t, ir.MemRefType) and math.prod(t.shape) == 1","tryCatchPattern":null,"preventionTips":["One 0-d i32 smem slot per tmem.alloc call","Never batch alloc addresses into an array memref"],"tags":["jax","mosaic","tmem","memref","shape-validation"],"backgroundTag":"shape-validation-failed","analyzedSha":"1e1c6a8fc06dfcd1247076ec5cae4640cea5d7bb","analyzedAt":"2026-08-27T09:53:25.647Z","schemaVersion":2},"datasetVersion":"2026-08-27T13:17:12.746Z"}