{"record":{"id":"51cff1d858e86666","repo":"rust-lang/rust","slug":"funnel-shift-on","errorCode":null,"errorMessage":"funnel shift on {:?}","messagePattern":"funnel shift on (.+?)","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"compiler/rustc_codegen_gcc/src/intrinsic/simd.rs","lineNumber":1709,"sourceCode":"    let vector_type = a_type.unqualified().dyncast_vector().expect(\"vector type\");\n    let num_units = vector_type.get_num_units();\n    let elem_type = vector_type.get_element_type();\n\n    let (new_int_type, int_shift_val, int_mask) = if elem_type.is_compatible_with(bx.u8_type)\n        || elem_type.is_compatible_with(bx.i8_type)\n    {\n        (bx.u16_type, 8, u8::MAX as u64)\n    } else if elem_type.is_compatible_with(bx.u16_type) || elem_type.is_compatible_with(bx.i16_type)\n    {\n        (bx.u32_type, 16, u16::MAX as u64)\n    } else if elem_type.is_compatible_with(bx.u32_type) || elem_type.is_compatible_with(bx.i32_type)\n    {\n        (bx.u64_type, 32, u32::MAX as u64)\n    } else if elem_type.is_compatible_with(bx.u64_type) || elem_type.is_compatible_with(bx.i64_type)\n    {\n        (bx.u128_type, 64, u64::MAX)\n    } else {\n        unimplemented!(\"funnel shift on {:?}\", elem_type);\n    };\n\n    let int_mask = bx.context.new_rvalue_from_long(new_int_type, int_mask as i64);\n    let int_shift_val = bx.context.new_rvalue_from_int(new_int_type, int_shift_val);\n    let mut elements = vec![];\n    let unsigned_type = elem_type.to_unsigned(bx);\n    for i in 0..num_units {\n        let index = bx.context.new_rvalue_from_int(bx.int_type, i as i32);\n        let a_val = bx.context.new_vector_access(None, a, index).to_rvalue();\n        let a_val = bx.context.new_bitcast(None, a_val, unsigned_type);\n        let a_val = bx.gcc_int_cast(a_val, new_int_type);\n        let b_val = bx.context.new_vector_access(None, b, index).to_rvalue();\n        let b_val = bx.context.new_bitcast(None, b_val, unsigned_type);\n        let b_val = bx.gcc_int_cast(b_val, new_int_type);\n        let shift_val = bx.context.new_vector_access(None, shift, index).to_rvalue();\n        let shift_val = bx.gcc_int_cast(shift_val, new_int_type);\n        let mut val = a_val << int_shift_val | b_val;\n        if shift_left {","sourceCodeStart":1691,"sourceCodeEnd":1727,"githubUrl":"https://github.com/rust-lang/rust/blob/7088e4b63a9516ebfbfe2ab2d999cf01a528ac14/compiler/rustc_codegen_gcc/src/intrinsic/simd.rs#L1691-L1727","documentation":"An `unimplemented!(\"funnel shift on {:?}\", elem_type)` ICE inside `simd_funnel_shift` in rustc_codegen_gcc (master-feature path). The function lowers SIMD funnel-shift to a scalar loop but only supports vector element widths 8/16/32/64 bits. A vector whose element type is none of those (e.g. 128-bit integers, or a non-integer element) reaches the `else` branch and panics.","triggerScenarios":"Invoking a SIMD funnel-shift intrinsic (`simd_shl`/`simd_shr` funnel forms) on a SIMD vector whose lane type is `i128`/`u128`, a float, or any type not matching `u8/i8/u16/i16/u32/i32/u64/i64`, while compiling with cg_gcc (master).","commonSituations":"Portable-SIMD code that performs funnel/rotate-shift on unusual lane widths (128-bit integer lanes), or where type inference produces an unexpected element type, combined with the GCC backend.","solutions":["Use LLVM backend for funnel shifts on non-standard lane widths.","Ensure the SIMD vector's lane type is one of i8..i64 / u8..u64 — widen/narrow explicitly before the funnel shift.","If 128-bit funnel shift is required, decompose it manually into 64-bit operations so it stays within supported element widths."],"exampleFix":"// before (cg_gcc, funnel shift on u128 lanes -> ICE)\nlet r: Simd<u128, 4> = unsafe { simd_shl(a, b, shift) };\n\n// after — LLVM backend, or restrict lanes to u64\nlet a64 = a.cast::<u64>(); // operate on supported lane width","handlingStrategy":"validation","validationCode":"# Funnel shift only supports i8..i64 / u8..u64 lanes in cg_gcc\n# In review, reject funnel/rotate shifts on u128/i128 lanes when targeting cg_gcc\nrg -n 'simd_(shl|shr)|rotate_left|rotate_right' src/  # audit lane widths","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Keep SIMD funnel/rotate-shift lane widths in {8,16,32,64}-bit integer ranges under cg_gcc.","Cast wide integer lanes to u64 before funnel shifting.","Use LLVM for funnel shifts on 128-bit or non-integer lanes."],"tags":["rustc","codegen-gcc","simd","funnel-shift","ice","compiler-internal"],"backgroundTag":null,"analyzedSha":"7088e4b63a9516ebfbfe2ab2d999cf01a528ac14","analyzedAt":"2026-08-10T14:17:03.603Z","contentChangedAt":null,"schemaVersion":2},"datasetVersion":"2026-09-14T00:17:10.932Z"}