{"record":{"id":"52bdb9b610badb47","repo":"embassy-rs/embassy","slug":"pll1-q-not-configured","errorCode":null,"errorMessage":"PLL1.Q not configured","messagePattern":"PLL1\\.Q not configured","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/rcc/wba.rs","lineNumber":423,"sourceCode":"            Hertz(24_000_000) => Usbrefcksel::Mhz24,\n            Hertz(26_000_000) => Usbrefcksel::Mhz26,\n            Hertz(32_000_000) => Usbrefcksel::Mhz32,\n            _ => panic!(\n                \"cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz\",\n                clk_val\n            ),\n        },\n        None => Usbrefcksel::Mhz24,\n    };\n    #[cfg(all(stm32wba, peri_usb_otg_hs))]\n    SYSCFG.otghsphycr().modify(|w| {\n        w.set_clksel(usb_refck_sel);\n    });\n\n    #[cfg(sai_v4_2pdm)]\n    let audioclk = match config.mux.sai1sel {\n        Sai1sel::Hsi => Some(HSI_FREQ),\n        Sai1sel::Pll1Q => Some(pll1.q.expect(\"PLL1.Q not configured\")),\n        Sai1sel::Pll1P => Some(pll1.p.expect(\"PLL1.P not configured\")),\n        Sai1sel::Sys => panic!(\"SYS not supported yet\"),\n        Sai1sel::Audioclk => panic!(\"AUDIOCLK not supported yet\"),\n        _ => None,\n    };\n\n    let lsi = config.ls.lsi.then_some(LSI_FREQ);\n    let lse = config.ls.lse.map(|c| c.frequency);\n\n    // Disable HSI if not used\n    if !config.hsi {\n        assert!(\n            config.mux.rngsel != mux::Rngsel::Hsi,\n            \"RNG is configured to use HSI but HSI is disabled\"\n        );\n        RCC.cr().modify(|w| w.set_hsion(false));\n    }\n","sourceCodeStart":405,"sourceCodeEnd":441,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/rcc/wba.rs#L405-L441","documentation":"In the STM32WBA rcc `init`, when SAI1 is muxed to `Pll1Q` (`sai1sel: Sai1sel::Pll1Q`) the code does `pll1.q.expect(\"PLL1.Q not configured\")`, panicking if PLL1's Q (and Q-div) output was never configured. The library needs a concrete audioclk frequency to program the SAI clock tree and cannot synthesize one.","triggerScenarios":"Setting `config.mux.sai1sel = Sai1sel::Pll1Q` in rcc config while `config.pll1.q` (Pll1QDiv and frequency fields) is `None`.","commonSituations":"Selecting a PLL1 Q audio clock without defining PLL1's Q output; copying an SAI audio config where the other board used PLL1P or HSI; incomplete pll1 setup (only P configured).","solutions":["Configure PLL1's Q output in the rcc config: `pll1: { q: Some(PllConfig { div: ..., freq: ... }) }`","Or choose a different SAI1 clock source that is actually configured (e.g. Hsi)","Verify the resulting audioclk frequency meets your audio sample-rate requirements"],"exampleFix":"// before\nlet config = rcc::Config { mux: rcc::mux::Sai1sel::Pll1Q, pll1: Pll1 { p: Some(..), q: None, .. } };\n// after\nlet config = rcc::Config {\n    mux: rcc::mux::Sai1sel::Pll1Q,\n    pll1: Pll1 { p: Some(..), q: Some(PllConfig { div: 4, freq: Hertz(49_152_000) }), .. },\n    ..\n};","handlingStrategy":"validation","validationCode":"if config.mux.sai1sel == rcc::mux::Sai1sel::Pll1Q && config.pll1.q.is_none() {\n    panic!(\"sai1sel=Pll1Q requires config.pll1.q to be configured\");\n}","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Whenever a mux selects a PLL output, configure that PLL output's freq/div","Match SAI clock source choice to the PLL1 outputs you actually defined","Test audio init on hardware before adding panel/peripheral init"],"tags":["embedded","rcc","pll","sai","panic"],"backgroundTag":"missing-required-config-field","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}