{"record":{"id":"57bf433cb8d46d47","repo":"embassy-rs/embassy","slug":"cannot-select-otg-hs-reference-clock-with-source-f-57bf43","errorCode":null,"errorMessage":"cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz","messagePattern":"cannot select OTG_HS reference clock with source frequency of (.+?), must be one of 16, 19\\.2, 20, 24, 26, 32 MHz","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/rcc/wba.rs","lineNumber":408,"sourceCode":"    let hclk5 = sys_clk / config.ahb5_pre;\n\n    #[cfg(all(stm32wba, peri_usb_otg_hs))]\n    let usb_refck = match config.mux.otghssel {\n        Otghssel::Hse => hse,\n        Otghssel::HseDiv2 => hse.map(|hse_val| hse_val / 2u8),\n        Otghssel::Pll1P => pll1.p,\n        Otghssel::Pll1PDiv2 => pll1.p.map(|pll1p_val| pll1p_val / 2u8),\n    };\n    #[cfg(all(stm32wba, peri_usb_otg_hs))]\n    let usb_refck_sel = match usb_refck {\n        Some(clk_val) => match clk_val {\n            Hertz(16_000_000) => Usbrefcksel::Mhz16,\n            Hertz(19_200_000) => Usbrefcksel::Mhz192,\n            Hertz(20_000_000) => Usbrefcksel::Mhz20,\n            Hertz(24_000_000) => Usbrefcksel::Mhz24,\n            Hertz(26_000_000) => Usbrefcksel::Mhz26,\n            Hertz(32_000_000) => Usbrefcksel::Mhz32,\n            _ => panic!(\n                \"cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz\",\n                clk_val\n            ),\n        },\n        None => Usbrefcksel::Mhz24,\n    };\n    #[cfg(all(stm32wba, peri_usb_otg_hs))]\n    SYSCFG.otghsphycr().modify(|w| {\n        w.set_clksel(usb_refck_sel);\n    });\n\n    #[cfg(sai_v4_2pdm)]\n    let audioclk = match config.mux.sai1sel {\n        Sai1sel::Hsi => Some(HSI_FREQ),\n        Sai1sel::Pll1Q => Some(pll1.q.expect(\"PLL1.Q not configured\")),\n        Sai1sel::Pll1P => Some(pll1.p.expect(\"PLL1.P not configured\")),\n        Sai1sel::Sys => panic!(\"SYS not supported yet\"),\n        Sai1sel::Audioclk => panic!(\"AUDIOCLK not supported yet\"),","sourceCodeStart":390,"sourceCodeEnd":426,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/rcc/wba.rs#L390-L426","documentation":"On STM32WBA, the OTG_HS USB reference clock selector only accepts sources of 16, 19.2, 20, 24, 26, or 32 MHz (Usbrefcksel field). embassy-stm32's RCC init panics when config.usb_refck names a source whose frequency falls outside this set, because no hardware selector value exists for it.","triggerScenarios":"rcc init with config.usb_refck = Some(...) where the selected source clock (PLL output, HSE-derived, etc.) is not exactly one of the six supported frequencies.","commonSituations":"Pointing usb_refck at a PLL Q output of e.g. 48 or 60 MHz; porting a U5 clock tree to WBA with different PLL settings; external oscillator frequencies not in the supported list.","solutions":["Retune the PLL (Q/dividers) so the usb_refck source is exactly 16, 19.2, 20, 24, 26, or 32 MHz","Or omit usb_refck (None), which selects the default 24 MHz option","Pick a different configured clock source that already runs at a supported frequency"],"exampleFix":"// before\nconfig.usb_refck = Some(UsbRefCkConfig { source: UsbRefCkSource::Pll1Q }); // PLL1.Q = 40 MHz -> panic\n// after\n// adjust PLL1 dividers so PLL1.Q = 32 MHz, then:\nconfig.usb_refck = Some(UsbRefCkConfig { source: UsbRefCkSource::Pll1Q });","handlingStrategy":"validation","validationCode":"const SUPPORTED: [u32; 6] = [16_000_000, 19_200_000, 20_000_000, 24_000_000, 26_000_000, 32_000_000];\nif let Some(refck) = &config.usb_refck {\n    let f = resolve_freq(refck.source); // your clock tree resolution\n    assert!(SUPPORTED.contains(&f), \"OTG_HS refck source {} Hz unsupported\", f);\n}","typeGuard":"fn is_valid_usb_refck_freq(hz: u32) -> bool {\n    matches!(hz, 16_000_000 | 19_200_000 | 20_000_000 | 24_000_000 | 26_000_000 | 32_000_000)\n}","tryCatchPattern":null,"preventionTips":["Design the PLL tree so a Q output lands on a supported frequency","Use None for usb_refck to accept the 24 MHz default","Validate the whole clock tree numerically before flashing","Cross-check USB clock settings against WBA reference manual"],"tags":["rust","embedded","stm32","wba","rcc","usb"],"backgroundTag":"value-out-of-range","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}