{"record":{"id":"60f0eca8386dab17","repo":"embassy-rs/embassy","slug":"maximal-allowed-frequency-for-the-adc-is-mhz-an-60f0ec","errorCode":null,"errorMessage":"Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.","messagePattern":"Maximal allowed frequency for the ADC is (.+?) MHz and it varies with different packages, refer to ST docs for more information\\.","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/adc/g4.rs","lineNumber":305,"sourceCode":"        // Clear JEOS by writing 1\n        self.isr().modify(|r| r.set_jeos(true));\n    }\n}\n\nimpl<'d, T: DefaultInstance> Adc<'d, T> {\n    /// Create a new ADC driver.\n    pub fn new(adc: Peri<'d, T>, config: AdcConfig) -> Self {\n        rcc::enable_and_reset::<T>();\n\n        let prescaler = from_ker_ck(T::frequency());\n\n        T::common_regs().ccr().modify(|w| w.set_presc(prescaler));\n\n        let frequency = T::frequency() / prescaler;\n        trace!(\"ADC frequency set to {}\", frequency);\n\n        if frequency > MAX_ADC_CLK_FREQ {\n            panic!(\n                \"Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.\",\n                MAX_ADC_CLK_FREQ.0 / 1_000_000\n            );\n        }\n\n        T::regs().cr().modify(|reg| {\n            reg.set_deeppwd(false);\n            reg.set_advregen(true);\n        });\n\n        block_for_us(20);\n\n        T::regs().difsel().modify(|w| {\n            for n in 0..18 {\n                w.set_difsel(n, Difsel::SingleEnded);\n            }\n        });\n","sourceCodeStart":287,"sourceCodeEnd":323,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/adc/g4.rs#L287-L323","documentation":"The G4-series ADC driver sets a prescaler on the ADC common clock register (CCR.PRESC) and computes the resulting frequency. If the ADC clock frequency still exceeds MAX_ADC_CLK_FREQ, the constructor panics, since running the ADC above its rated clock violates the ST datasheet and degrades conversion accuracy. The limit varies per package/voltage, so ST's docs are referenced.","triggerScenarios":"Calling `Adc::new(...)` for an STM32G4 target when T::frequency() (the ADC kernel clock, e.g. from RCC's AdcClockSource) exceeds MAX_ADC_CLK_FREQ even after the driver sets CCR prescaler bits.","commonSituations":"Configuring the ADC kernel clock to PLL \"P\" output at a high rate and forgetting the ADC prescaler; running at 170 MHz with AHB/1 mapped to ADC; copying clock setup from another G4 board with different crystal/PLL values.","solutions":["Set RCC adc_clock_source / ADC prescaler so the ADC clock is within MAX_ADC_CLK_FREQ (G4 max typically 60 MHz on VREF>=2.7V, lower on reduced voltage)","Choose a slower kernel clock source (e.g. HCLK divided or HSI) in the RCC config","Check ST's G4 datasheet for the frequency limit at your operating voltage and adjust SYSCLK/PLL accordingly"],"exampleFix":"// before\nconfig.rcc.adc_clock_source = AdcClockSource::Pll(SP::P); // 170MHz too fast\n// after\nconfig.rcc.adc_clock_source = AdcClockSource::Pll(SP::P);\nconfig.rcc.adc_prescaler = AdcPrescaler::DividedBy4; // <= MAX_ADC_CLK_FREQ","handlingStrategy":"validation","validationCode":"let adc_clk_hz = adc_kernel_clock_hz(); // e.g. PLLP or HCLK derived\n// G4: max 60 MHz (VREF >= 2.7V), less at lower voltage\nassert!(adc_clk_hz <= MAX_ADC_CLK_FREQ_HZ, \"ADC clock too high: {} Hz\", adc_clk_hz);","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Set the CCR prescaler explicitly in RCC config rather than relying on defaults","Remember G4 limits scale with VREF voltage","Derive ADC clock from a divided source, not raw PLL output","Print computed ADC frequency during development"],"tags":["embedded","stm32","adc","clock-config","rust"],"backgroundTag":"value-out-of-range","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}