{"record":{"id":"6ca1f82d30014519","repo":"embassy-rs/embassy","slug":"dma-error-on-mdma-08x-channel","errorCode":null,"errorMessage":"DMA: error on MDMA@{:08x} channel {}","messagePattern":"DMA: error on MDMA@(.+?) channel (.+?)","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"critical","filePath":"embassy-stm32/src/dma/dma_bdma.rs","lineNumber":90,"sourceCode":"            }\n            if !activity {\n                return;\n            }\n\n            state.waker.wake();\n        }\n        #[cfg(mdma)]\n        DmaInfo::Mdma(r) => {\n            // If our bit in gisr0 is not set, then the interrupt is not for this channel\n            if !r.gisr0().read().gif(info.num) {\n                return;\n            }\n\n            let isr = r.ch(info.num).isr();\n            let ifcr = r.ch(info.num).ifcr();\n\n            if isr.read().teif() {\n                panic!(\"DMA: error on MDMA@{:08x} channel {}\", r.as_ptr() as u32, info.num);\n            }\n\n            if isr.read().ctcif() {\n                // Channel Transfer complete\n                state.complete_count.fetch_add(1, Ordering::Release);\n                ifcr.write(|w| w.set_cctcif(true));\n            }\n\n            state.waker.wake();\n        }\n    }\n}\n\npub(crate) struct ChannelInfo {\n    pub(crate) dma: DmaInfo,\n    pub(crate) num: usize,\n    #[cfg(feature = \"_dual-core\")]\n    pub(crate) irq: pac::Interrupt,","sourceCodeStart":72,"sourceCodeEnd":108,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/dma/dma_bdma.rs#L72-L108","documentation":"The MDMA (master DMA) interrupt handler panics when the channel's transfer-error flag (teif) is set. MDMA is a high-throughput master DMA that can service memory-to-memory and peripheral-to-memory transfers; a transfer error indicates an illegal or failing bus access for the configured channel.","triggerScenarios":"on_irq for an MDMA channel reads isr.teif() true — e.g. source/destination address in a region MDMA cannot access, bus contention/fault, or misconfigured burst/transfer size on an MDMA channel operation.","commonSituations":"Memory-to-memory copy into DTCM/ITCM regions not reachable by MDMA on some parts; invalid SWRM (software request) configuration; buffer alignment smaller than the configured burst size; attempting to write to read-only memory regions.","solutions":["Validate source and destination addresses are in MDMA-accessible memory; move buffers out of DTCM/ITCM if the chip's MDMA cannot reach them.","Check the transfer configuration: data size, burst size, and buffer alignment must be consistent.","Confirm the SWRM request number and trigger selection match the intended operation.","Reproduce with a minimal memory-to-memory MDMA copy to isolate whether the peripheral or the memory region is at fault."],"exampleFix":"// before\nstatic mut DST: [u8; 256] = [0; 256]; // in DTCM, unreachable by MDMA\nmdma.copy(&SRC, &mut DST).await;\n\n// after\nstatic mut DST: [u8; 256] = [0; 256]; // placed in AXI SRAM via linker section\nmdma.copy(&SRC, &mut DST).await;","handlingStrategy":"validation","validationCode":"// Validate MDMA targets before the copy:\nlet ok = |addr: u32| (0x2400_0000..0x2405_0000).contains(&addr); // AXI SRAM example\nassert!(ok(src.as_ptr() as u32) && ok(dst.as_ptr() as u32), \"MDMA cannot access one of the buffers\");","typeGuard":"fn mdma_accessible<T>(buf: &[T]) -> bool {\n    let addr = buf.as_ptr() as u32;\n    // Adjust per chip: MDMA usually reaches AXI SRAM, not DTCM/ITCM on all parts\n    (0x2400_0000..0x2405_0000).contains(&addr)\n}","tryCatchPattern":"// IRQ panic is unrecoverable; validate before starting:\nassert!(mdma_accessible(&dst) && mdma_accessible(&src), \"invalid MDMA buffer placement\");","preventionTips":["Link MDMA buffers into AXI SRAM or other MDMA-reachable regions; avoid DTCM/ITCM unless the reference manual confirms access.","Match burst size and data size to buffer alignment.","Test with a minimal memory-to-memory MDMA transfer when bringing up a new chip/board.","Avoid targeting read-only or peripheral-reserved regions with MDMA writes."],"tags":["embedded","dma","mdma","panic","interrupt"],"backgroundTag":"invalid-config-value","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}