{"record":{"id":"72eeb14c3e133999","repo":"embassy-rs/embassy","slug":"unknown-cortex-m-core","errorCode":null,"errorMessage":"Unknown Cortex-M core","messagePattern":"Unknown Cortex-M core","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"critical","filePath":"embassy-stm32/src/cpu.rs","lineNumber":42,"sourceCode":"\nimpl CoreId {\n    /// Get the current core id\n    /// This code assume that it is only executed on a Cortex-M M0+, M4 or M7 core.\n    pub fn current() -> Self {\n        let cpuid = unsafe { cortex_m::peripheral::CPUID::PTR.read_volatile().base.read() };\n        match (cpuid & 0x000000F0) >> 4 {\n            #[cfg(any(stm32wb, stm32wl))]\n            0x0 => CoreId::Core1,\n\n            #[cfg(not(any(stm32h745, stm32h747, stm32h755, stm32h757)))]\n            0x4 => CoreId::Core0,\n\n            #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757))]\n            0x4 => CoreId::Core1,\n\n            #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757))]\n            0x7 => CoreId::Core0,\n            _ => panic!(\"Unknown Cortex-M core\"),\n        }\n    }\n\n    #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757, stm32wb, stm32wl))]\n    /// Get the other core id\n    pub const fn other(&self) -> Self {\n        match &self {\n            Self::Core0 => Self::Core1,\n            Self::Core1 => Self::Core0,\n        }\n    }\n\n    /// Translates the core ID to an index into the interrupt registers.\n    pub const fn to_index(&self) -> u8 {\n        match &self {\n            CoreId::Core0 => 0,\n            #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757, stm32wb, stm32wl))]\n            CoreId::Core1 => 1,","sourceCodeStart":24,"sourceCodeEnd":60,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/cpu.rs#L24-L60","documentation":"cpu::current() reads the CPU id register to map the executing processor to a CoreId. Only specific CPU-id values (0x4/0x7 for dual-core H7 parts) are handled; any other value panics. This means code is running on a core — or under an emulator — whose CPU id does not match any value the HAL recognizes for this chip family.","triggerScenarios":"Calling cpu::current() on a dual-core part (stm32h745/747/755/757, wb, wl) when the CPU id is not one of the recognized values: e.g. code linked for Core1 executing on Core0 (or vice versa), or an emulator reporting a nonstandard id.","commonSituations":"Running dual-core H7 firmware under QEMU/emulation with nonstandard MPIDR; feature flags not matching the actual silicon variant; a bootloader/boot RCC configuration starting the image on the wrong core.","solutions":["Verify the firmware is booted on the intended core (check boot address / RCC CPU boot configuration for H7 dual-core parts).","Check that the selected chip features match the actual STM32 variant so the correct CPU-id mappings are compiled in.","If running under an emulator, use real hardware or an emulator model with correct CPU id values."],"exampleFix":null,"handlingStrategy":"validation","validationCode":"// Only use per-core APIs on the intended core; verify boot address maps\n// this image to the core whose CPU id the HAL expects.\nlet cpu_id = /* read CPU id register */;\nassert!(matches!(cpu_id, 0x4 | 0x7), \"unexpected core id\");","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Pin firmware to its target core via boot address linker config","Assert chip variant features in CI builds","Avoid per-core APIs in shared code without matching CPU ids"],"tags":["embedded","cortex-m","dual-core","panic"],"backgroundTag":"unsupported-platform","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-23T08:17:48.524Z"}