{"record":{"id":"841ac097f67f2be7","repo":"rust-lang/rust","slug":"simd","errorCode":null,"errorMessage":"simd {}","messagePattern":"simd \\{\\}","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"compiler/rustc_codegen_gcc/src/intrinsic/simd.rs","lineNumber":1677,"sourceCode":"            let after_block = bx.current_func().new_block(\"after\");\n            let then_block = bx.current_func().new_block(\"then\");\n            bx.llbb().end_with_conditional(None, mask, then_block, after_block);\n\n            bx.switch_to_block(then_block);\n            let lvalue = bx.context.new_array_access(None, pointer, i);\n            let value = bx.context.new_vector_access(None, values, i).to_rvalue();\n            bx.llbb().add_assignment(None, lvalue, value);\n            bx.llbb().end_with_jump(None, after_block);\n\n            bx.switch_to_block(after_block);\n        }\n\n        let dummy_value = bx.context.new_rvalue_zero(bx.int_type);\n\n        return Ok(dummy_value);\n    }\n\n    unimplemented!(\"simd {}\", name);\n}\n\n#[cfg(feature = \"master\")]\nfn simd_funnel_shift<'a, 'gcc, 'tcx>(\n    bx: &mut Builder<'a, 'gcc, 'tcx>,\n    a: RValue<'gcc>,\n    b: RValue<'gcc>,\n    shift: RValue<'gcc>,\n    shift_left: bool,\n) -> RValue<'gcc> {\n    use crate::common::SignType;\n\n    let a_type = a.get_type();\n    let vector_type = a_type.unqualified().dyncast_vector().expect(\"vector type\");\n    let num_units = vector_type.get_num_units();\n    let elem_type = vector_type.get_element_type();\n\n    let (new_int_type, int_shift_val, int_mask) = if elem_type.is_compatible_with(bx.u8_type)","sourceCodeStart":1659,"sourceCodeEnd":1695,"githubUrl":"https://github.com/rust-lang/rust/blob/7088e4b63a9516ebfbfe2ab2d999cf01a528ac14/compiler/rustc_codegen_gcc/src/intrinsic/simd.rs#L1659-L1695","documentation":"An `unimplemented!(\"simd {}\", name)` ICE at the end of `generic_simd_intrinsic` in rustc_codegen_gcc (non-master branch context). After all recognized `simd_*` intrinsic names are matched, any unmatched SIMD intrinsic name reaches this line and panics. It represents an unfinished SIMD intrinsic in the GCC backend's SIMD-lowering table.","triggerScenarios":"Calling a `core::intrinsics::simd_*` intrinsic (directly or via `std::simd` / portable-simd style code) whose `name` symbol is not handled by any earlier `#[cfg(feature = \"master\")]` branch in `generic_simd_intrinsic`, when compiling with cg_gcc. The remaining fallthrough at simd.rs:1677 fires.","commonSituations":"Using nightly `std::simd` / portable SIMD or hand-written `simd_*` intrinsics while the GCC backend is enabled and the particular intrinsic (e.g. a recently added one) is missing from cg_gcc's match list.","solutions":["Compile the same crate with the LLVM backend, which has complete SIMD intrinsic coverage.","Rebuild cg_gcc from a tree that includes the `#[cfg(feature = \"master\")]` SIMD branches and verify the intrinsic name is matched.","Avoid the specific `simd_*` intrinsic reported in the panic message (`name`); substitute an equivalent portable operation."],"exampleFix":"// before (cg_gcc, unhandled simd intrinsic -> ICE)\nuse core::intrinsics::simd::simd_arith;\nlet r = unsafe { simd_arith(a, b) };\n\n// after — LLVM backend, or express via std::simd lanes\nlet r = a + b; // Simd<...> supports operator overloading","handlingStrategy":"fallback","validationCode":"# Detect portable-simd / simd intrinsics + gcc backend\nif grep -rqE 'std::simd|core::intrinsics::simd|simd_' src/ && [[ \"${RUSTFLAGS:-}\" == *codegen-backend=gcc* ]]; then\n  echo \"avoid: cg_gcc SIMD table may be missing some intrinsics; use LLVM or rebuild with master\"\nfi","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Use the LLVM backend for `std::simd` / portable-simd code.","Rebuild cg_gcc from a current tree with the master feature so the SIMD branches are compiled in.","Note the exact `simd_*` name in the ICE and check it against cg_gcc's match list."],"tags":["rustc","codegen-gcc","simd","portable-simd","ice","compiler-internal","nightly"],"backgroundTag":null,"analyzedSha":"7088e4b63a9516ebfbfe2ab2d999cf01a528ac14","analyzedAt":"2026-08-10T14:17:03.603Z","contentChangedAt":null,"schemaVersion":2},"datasetVersion":"2026-09-14T00:17:10.932Z"}