{"record":{"id":"a1eecdf1a089a1d2","repo":"sgl-project/sglang","slug":"simm-register-buffer-error","errorCode":null,"errorMessage":"SiMM Register Buffer Error.","messagePattern":"SiMM Register Buffer Error\\.","errorType":"exception","errorClass":"TypeError","httpStatus":null,"severity":"error","filePath":"python/sglang/srt/mem_cache/storage/simm/hicache_simm.py","lineNumber":261,"sourceCode":"        )\n\n    def register_mem_pool_host(self, mem_pool_host: HostKVCache):\n        super().register_mem_pool_host(mem_pool_host)\n        assert self.mem_pool_host.layout in [\n            \"page_first\",\n            \"page_first_direct\",\n        ], \"simm storage backend only support page first or page first direct layout\"\n        buffer = self.mem_pool_host.kv_buffer\n        try:\n            self.mr_ext = register_mr(buffer)\n            if self.mr_ext is None:\n                logger.error(\n                    f\"Failed to register buffer, {buffer=}, please check buffer and RDMA network\"\n                )\n                raise RuntimeError(f\"Failed to register buffer to SiMM\")\n        except TypeError as err:\n            logger.error(\"Failed to register buffer to SiMM: %s\", err)\n            raise TypeError(\"SiMM Register Buffer Error.\") from err\n\n    def _get_mha_buffer_meta(self, keys, indices):\n        ptr_list, element_size_list = self.mem_pool_host.get_page_buffer_meta(indices)\n        key_list = []\n        for key_ in keys:\n            key_list.append(f\"{key_}_{self.mha_suffix}_k\")\n            key_list.append(f\"{key_}_{self.mha_suffix}_v\")\n        if len(key_list) != len(ptr_list):\n            logger.error(\n                f\"key size {len(key_list)} not equal with incides ptr size {len(ptr_list)}\"\n            )\n        assert len(key_list) == len(ptr_list)\n        return key_list, ptr_list, element_size_list\n\n    def _get_mla_buffer_meta(self, keys, indices):\n        ptr_list, element_size_list = self.mem_pool_host.get_page_buffer_meta(indices)\n        key_list = []\n        for key_ in keys:","sourceCodeStart":243,"sourceCodeEnd":279,"githubUrl":"https://github.com/sgl-project/sglang/blob/0132848349585cfe6aae51c4941cbae872505f8a/python/sglang/srt/mem_cache/storage/simm/hicache_simm.py#L243-L279","documentation":"A TypeError raised while registering a host buffer to SiMM — the register_mr call itself raised TypeError, typically because the buffer has an unexpected type/shape unsupported by the SiMM registration API. The original exception is chained via 'from err'.","triggerScenarios":"Calling register_mem_pool_host with a buffer whose type register_mr does not accept (e.g. a numpy array, list, or tensor with unsupported dtype/layout), producing a TypeError inside register_mr.","commonSituations":"Version mismatch between the installed mori/SiMM wheel and sglang's expected buffer API; passing a pool buffer allocated with a non-standard allocator.","solutions":["Check the logged chained error ('Failed to register buffer to SiMM: %s') for the exact argument mismatch","Match mori/SiMM version to the sglang release requirements and reinstall","Ensure the buffer is a torch CPU tensor allocated by the host mem pool allocator","If the type is genuinely unsupported upstream, report/fallback to the default host allocator"],"exampleFix":"// before\nstore.register_mem_pool_host(np_array)\n// after\nstore.register_mem_pool_host(torch.from_numpy(np_array))  # torch CPU tensor expected","handlingStrategy":"try-catch","validationCode":"import torch\nassert isinstance(buffer, torch.Tensor), f'expected torch.Tensor, got {type(buffer)}'","typeGuard":"def is_supported_buffer_type(b) -> bool:\n    import torch\n    return isinstance(b, torch.Tensor)","tryCatchPattern":"try:\n    store.register_mem_pool_host(buf)\nexcept TypeError as e:\n    if 'SiMM Register Buffer' in str(e):\n        buf = torch.as_tensor(buf)\n        store.register_mem_pool_host(buf)  # retry with converted type","preventionTips":["Convert buffers to torch CPU tensors at pool boundaries","Pin mori/SiMM version compatible with your sglang release","Write unit tests asserting buffer types before registration"],"tags":["rdma","type-error","sim","memory-registration"],"backgroundTag":"invalid-argument-type","analyzedSha":"0132848349585cfe6aae51c4941cbae872505f8a","analyzedAt":"2026-08-28T05:10:05.995Z","schemaVersion":2},"datasetVersion":"2026-08-28T06:17:29.519Z"}