{"record":{"id":"a42a7cd9a9568ae2","repo":"wasmerio/wasmer","slug":"not-yet-implemented-a42a7c","errorCode":null,"errorMessage":"not yet implemented","messagePattern":"not yet implemented","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"lib/compiler-singlepass/src/emitter_riscv.rs","lineNumber":354,"sourceCode":"    fn emit_load_label(&mut self, reg: GPR, label: Label) -> Result<(), CompileError>;\n    fn emit_call_label(&mut self, label: Label) -> Result<(), CompileError>;\n    fn emit_call_register(&mut self, reg: GPR) -> Result<(), CompileError>;\n\n    fn emit_rwfence(&mut self) -> Result<(), CompileError>;\n    fn emit_atomic_binop(\n        &mut self,\n        op: AtomicBinaryOp,\n        size: Size,\n        dest: GPR,\n        addr: GPR,\n        source: GPR,\n    ) -> Result<(), CompileError>;\n    fn emit_reserved_ld(&mut self, size: Size, reg: GPR, addr: GPR) -> Result<(), CompileError>;\n}\n\nimpl EmitterRiscv for Assembler {\n    fn get_simd_arch(&self) -> Option<&CpuFeature> {\n        todo!()\n    }\n\n    fn get_label(&mut self) -> Label {\n        self.new_dynamic_label()\n    }\n\n    fn get_offset(&self) -> Offset {\n        self.offset()\n    }\n\n    fn get_jmp_instr_size(&self) -> u8 {\n        todo!()\n    }\n\n    fn finalize_function(&mut self) -> Result<(), CompileError> {\n        Ok(())\n    }\n","sourceCodeStart":336,"sourceCodeEnd":372,"githubUrl":"https://github.com/wasmerio/wasmer/blob/8c4b9ee9d33fb2068863fbb3d328683e7e6ff7f5/lib/compiler-singlepass/src/emitter_riscv.rs#L336-L372","documentation":"`get_simd_arch` on the RISC-V singlepass emitter is implemented as `todo!()`, meaning SIMD CPU-feature detection for RISC-V was never written. Any singlepass compilation path that queries the SIMD architecture on RISC-V panics with 'not yet implemented'. It indicates SIMD support is simply missing in the RISC-V backend.","triggerScenarios":"Running wasm SIMD (v128) code through wasmtime's singlepass RISC-V backend; anything that calls `get_simd_arch` (EmitterRiscv impl at emitter_riscv.rs:354).","commonSituations":"Deploying wasmtime on RISC-V (riscv64) hardware and compiling modules that use wasm SIMD; enabling wasm_simd in config on RISC-V singlepass.","solutions":["Disable wasm SIMD: config.wasm_simd(false) before creating the engine","Use the Cranelift backend on RISC-V instead of singlepass","Upgrade wasmtime to a version where RISC-V SIMD support landed","Avoid v128-using modules on RISC-V singlepass"],"exampleFix":"// before: singlepass on riscv64 + wasm simd -> panic\nlet mut config = Config::new();\nconfig.wasm_simd(true);\n// after: disable simd on riscv singlepass\nlet mut config = Config::new();\nconfig.wasm_simd(false); // or use Strategy::Cranelift","handlingStrategy":"validation","validationCode":"// On riscv64 singlepass, ensure SIMD is off before compiling.\nif cfg!(target_arch = \"riscv64\") {\n    config.wasm_simd(false);\n    config.wasm_relaxed_simd(false);\n}\n// Or validate that module has no v128 ops:\nlet mut features = WasmFeatures::default();\nfeatures.simd = false;\nwasmparser::Validator::new_with_features(features).validate_all(&wasm_bytes)?;","typeGuard":null,"tryCatchPattern":"let result = std::panic::catch_unwind(|| {\n    Module::new(&engine, &wasm_bytes)\n});\nmatch result {\n    Ok(Ok(m)) => m,\n    _ => return Err(CompileError::new(\"singlepass riscv: SIMD unsupported\")),\n}","preventionTips":["Disable wasm_simd on RISC-V singlepass targets","Prefer Cranelift strategy on riscv64","Test-compile SIMD-using modules per-target in CI"],"tags":["wasmtime","singlepass","riscv","simd","unimplemented"],"backgroundTag":"unimplemented-backend-feature","analyzedSha":"8c4b9ee9d33fb2068863fbb3d328683e7e6ff7f5","analyzedAt":"2026-09-01T23:06:31.009Z","contentChangedAt":null,"schemaVersion":2},"datasetVersion":"2026-09-09T06:17:21.866Z"}