{"record":{"id":"a5290dcc170b2540","repo":"embassy-rs/embassy","slug":"source-must-be-equal-across-all-enabled-plls","errorCode":null,"errorMessage":"Source must be equal across all enabled PLLs.","messagePattern":"Source must be equal across all enabled PLLs\\.","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/rcc/h.rs","lineNumber":538,"sourceCode":"    // Configure HSI48.\n    let hsi48 = config.hsi48.map(super::init_hsi48);\n\n    // Configure CSI.\n    RCC.cr().modify(|w| w.set_csion(config.csi));\n    let csi = match config.csi {\n        false => None,\n        true => {\n            while !RCC.cr().read().csirdy() {}\n            Some(CSI_FREQ)\n        }\n    };\n\n    // H7 has shared PLLSRC, check it's equal in all PLLs.\n    #[cfg(any(stm32h7, stm32h7rs))]\n    {\n        let plls = [&config.pll1, &config.pll2, &config.pll3];\n        if !super::util::all_equal(plls.into_iter().flatten().map(|p| p.source)) {\n            panic!(\"Source must be equal across all enabled PLLs.\")\n        };\n    }\n\n    // Configure PLLs.\n    let pll_input = PllInput { csi, hse, hsi };\n    disable_pll(0);\n    let pll1 = config\n        .pll1\n        .map_or_else(PllOutput::default, |c| init_pll(0, c, &pll_input));\n    disable_pll(1);\n    let pll2 = config\n        .pll2\n        .map_or_else(PllOutput::default, |c| init_pll(1, c, &pll_input));\n    #[cfg(any(rcc_h5, stm32h7, stm32h7rs))]\n    disable_pll(2);\n    #[cfg(any(rcc_h5, stm32h7, stm32h7rs))]\n    let pll3 = config\n        .pll3","sourceCodeStart":520,"sourceCodeEnd":556,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/rcc/h.rs#L520-L556","documentation":"On H7/H7RS the PLLSRC mux is a single shared register field feeding PLL1, PLL2 and PLL3, so all enabled PLLs must select the same source (HSE, HSI, or CSI). init checks this with all_equal and panics if two enabled PLLs disagree. Disabled PLLs (None) are ignored by the check.","triggerScenarios":"Passing a Config in which, e.g., pll1 uses PllSource::HSE and pll2 or pll3 uses PllSource::HSI (or CSI) on stm32h7/stm32h7rs; any combination of two or more Some(pll) entries with differing .source values.","commonSituations":"Individually copying per-PLL configs from datasheets without noticing they share one source mux; migrating configs from L4/F4 (independent sources) to H7; enabling a second PLL for SAI/USB with a 'more convenient' different source.","solutions":["Set the same PllSource on pll1, pll2 and pll3 (the ones that are Some) in the Config.","Use prediv (DIVM) per-PLL to derive the reference frequencies you need from the single shared source.","Verify with the clock tree that the shared source frequency supports all three PLL outputs."],"exampleFix":"// before\nlet config = Config {\n    pll1: Some(Pll { source: PllSource::HSE, ..Default::default() }),\n    pll3: Some(Pll { source: PllSource::CSI, ..Default::default() }),\n    ..Default::default()\n};\n// after\nlet config = Config {\n    pll1: Some(Pll { source: PllSource::HSE, ..Default::default() }),\n    pll3: Some(Pll { source: PllSource::HSE, ..Default::default() }),\n    ..Default::default()\n};","handlingStrategy":"validation","validationCode":"let sources: Vec<_> = [config.pll1.as_ref(), config.pll2.as_ref(), config.pll3.as_ref()]\n    .into_iter().flatten().map(|p| p.source).collect();\nassert!(sources.windows(2).all(|w| w[0] == w[1]), \"H7: all enabled PLLs must share one PLLSRC\");","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Treat PLLSRC as a board-level decision on H7; define it once and reuse in every PLL struct.","Use per-PLL DIVM/prediv for frequency shaping instead of different sources.","Re-check the clock tree after enabling additional PLLs (SAI, USB, SDMMC)."],"tags":["rust","embedded","rcc","pll","stm32h7"],"backgroundTag":"conflicting-config-options","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}