{"record":{"id":"a5cf8fa6576de248","repo":"embassy-rs/embassy","slug":"pll-vco-clk-out-of-range","errorCode":null,"errorMessage":"pll vco_clk out of range: {}","messagePattern":"pll vco_clk out of range: (.+?)","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/rcc/h.rs","lineNumber":998,"sourceCode":"    // be chosen when the reference clock frequency is lower than 2 MHz.\n    let wide_allowed = ref_range != Pllrge::Range1;\n\n    #[cfg(any(stm32h743, stm32h730))]\n    let vco_clk = match config.fracn {\n        Some(fracn) => {\n            Hertz::hz((ref_clk.0 as f32 * ((config.mul.to_bits() + 1) as f32 + (fracn as f32 / 8192.0))) as u32)\n        }\n        None => ref_clk * config.mul,\n    };\n    #[cfg(not(any(stm32h743, stm32h730)))]\n    let vco_clk = ref_clk * config.mul;\n\n    let vco_range = if VCO_RANGE.contains(&vco_clk) {\n        Pllvcosel::MediumVco\n    } else if wide_allowed && VCO_WIDE_RANGE.contains(&vco_clk) {\n        Pllvcosel::WideVco\n    } else {\n        panic!(\"pll vco_clk out of range: {}\", vco_clk)\n    };\n\n    let p = config.divp.map(|div| {\n        if num == 0 {\n            // on PLL1, DIVP must be even for most series.\n            // The enum value is 1 less than the divider, so check it's odd.\n            #[cfg(not(any(pwr_h7rm0468, stm32h7rs)))]\n            assert!(div.to_bits() % 2 == 1);\n            #[cfg(pwr_h7rm0468)]\n            assert!(div.to_bits() % 2 == 1 || div.to_bits() == 0);\n        }\n\n        vco_clk / div\n    });\n    let q = config.divq.map(|div| vco_clk / div);\n    let r = config.divr.map(|div| vco_clk / div);\n    #[cfg(stm32h7rs)]\n    let s = config.divs.map(|div| vco_clk / div);","sourceCodeStart":980,"sourceCodeEnd":1016,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/rcc/h.rs#L980-L1016","documentation":"The computed VCO output frequency (ref_clk * mul, after the feedback divider) must fit inside VCO_RANGE (medium VCO) or, when the reference range permits it, VCO_WIDE_RANGE (wide VCO). If vco_clk fits neither window, init_pll panics with the offending value, preventing an impossible hardware configuration.","triggerScenarios":"Configuring pll.mul so that ref_clk * mul falls between the two hardware VCO windows or above the wide-VCO max (e.g. a mid-range speed in the ~420 MHz gap, or beyond the wide limit). Also triggered by Range1 (ref_clk < 2 MHz), where wide mode is disallowed (wide_allowed == false).","commonSituations":"Tuning mul by hand for a specific target frequency and landing in the gap; using a very small prediv (<2 MHz reference) that forces medium VCO while mul requires wide range; miscomputed math after changing prediv.","solutions":["Adjust pll.mul so vco_clk lands inside VCO_RANGE (medium) — or inside VCO_WIDE_RANGE with a reference >= 2 MHz.","Raise prediv above the <2 MHz boundary if you need WideVco, so wide_allowed becomes true.","Recompute the output dividers (divp/divq/divr) to still hit your target peripheral clocks."],"exampleFix":"// before\n// ref_clk = 1.5 MHz (48MHz/32), mul = 300 -> vco 450 MHz; wide not allowed (Range1) -> panic\nlet pll = Pll { prediv: PllPreDiv::Div32, mul: Mul::Mul300, ..Default::default() };\n// after\nlet pll = Pll { prediv: PllPreDiv::Div8, mul: Mul::Mul75, ..Default::default() }; // ref 6 MHz, wide allowed","handlingStrategy":"validation","validationCode":"const VCO_MIN: u32 = 150_000_000; const VCO_MAX: u32 = 420_000_000; const VCO_WIDE_MAX: u32 = 832_000_000;\nlet vco = ref_hz * pll.mul as u32;\nlet in_medium = (VCO_MIN..=VCO_MAX).contains(&vco);\nlet in_wide = ref_hz >= 2_000_000 && (VCO_MIN..=VCO_WIDE_MAX).contains(&vco);\nassert!(in_medium || in_wide, \"vco {} Hz out of range\", vco);","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Keep ref_clk >= 2 MHz so wide-VCO mode is available when needed.","Solve for mul from the target VCO value instead of tuning by hand.","Re-derive output dividers whenever mul changes."],"tags":["rust","embedded","rcc","pll","frequency"],"backgroundTag":"value-out-of-range","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}