{"record":{"id":"a9a042994d0965ad","repo":"embassy-rs/embassy","slug":"pll1-p-not-configured","errorCode":null,"errorMessage":"PLL1.P not configured","messagePattern":"PLL1\\.P not configured","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/rcc/wba.rs","lineNumber":424,"sourceCode":"            Hertz(26_000_000) => Usbrefcksel::Mhz26,\n            Hertz(32_000_000) => Usbrefcksel::Mhz32,\n            _ => panic!(\n                \"cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz\",\n                clk_val\n            ),\n        },\n        None => Usbrefcksel::Mhz24,\n    };\n    #[cfg(all(stm32wba, peri_usb_otg_hs))]\n    SYSCFG.otghsphycr().modify(|w| {\n        w.set_clksel(usb_refck_sel);\n    });\n\n    #[cfg(sai_v4_2pdm)]\n    let audioclk = match config.mux.sai1sel {\n        Sai1sel::Hsi => Some(HSI_FREQ),\n        Sai1sel::Pll1Q => Some(pll1.q.expect(\"PLL1.Q not configured\")),\n        Sai1sel::Pll1P => Some(pll1.p.expect(\"PLL1.P not configured\")),\n        Sai1sel::Sys => panic!(\"SYS not supported yet\"),\n        Sai1sel::Audioclk => panic!(\"AUDIOCLK not supported yet\"),\n        _ => None,\n    };\n\n    let lsi = config.ls.lsi.then_some(LSI_FREQ);\n    let lse = config.ls.lse.map(|c| c.frequency);\n\n    // Disable HSI if not used\n    if !config.hsi {\n        assert!(\n            config.mux.rngsel != mux::Rngsel::Hsi,\n            \"RNG is configured to use HSI but HSI is disabled\"\n        );\n        RCC.cr().modify(|w| w.set_hsion(false));\n    }\n\n    config.mux.init();","sourceCodeStart":406,"sourceCodeEnd":442,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/rcc/wba.rs#L406-L442","documentation":"Same guard as PLL1.Q but for the P output: in STM32WBA rcc `init`, selecting `sai1sel: Sai1sel::Pll1P` runs `pll1.p.expect(\"PLL1.P not configured\")`, panicking when PLL1's P output was not configured. SAI1 muxed to PLL1P needs that PLL output to exist in the clock tree.","triggerScenarios":"Setting `config.mux.sai1sel = Sai1sel::Pll1P` while `config.pll1.p` is `None` (P frequency/div unset).","commonSituations":"Audio (SAI/I2S) init where PLL1 was configured only for SYSCLK via Q, leaving P undefined; templates that enable the PLL1P mux by default without enabling the PLL output.","solutions":["Configure `config.pll1.p` with the required frequency and divider for the audio clock","Switch `sai1sel` to a configured source (Hsi or Pll1Q if set up)","Cross-check the PLLP output against the SAI sample-rate clock requirement"],"exampleFix":"// before\nlet config = rcc::Config { mux: rcc::mux::Sai1sel::Pll1P, pll1: Pll1 { p: None, .. } };\n// after\nlet config = rcc::Config {\n    mux: rcc::mux::Sai1sel::Pll1P,\n    pll1: Pll1 { p: Some(PllConfig { div: 8, freq: Hertz(12_288_000) }), .. },\n    ..\n};","handlingStrategy":"validation","validationCode":"if config.mux.sai1sel == rcc::mux::Sai1sel::Pll1P && config.pll1.p.is_none() {\n    panic!(\"sai1sel=Pll1P requires config.pll1.p to be configured\");\n}","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Configure PLL1.P explicitly for audio clocking, not just PLL1.Q for sysclk","Use the WBA SAI example's PLL1 settings as a template","Audit mux selections against configured PLL outputs in code review"],"tags":["embedded","rcc","pll","sai","panic"],"backgroundTag":"missing-required-config-field","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}