{"record":{"id":"ad70ea3488ff756d","repo":"embassy-rs/embassy","slug":"invalid-ahb5-pre-for-hsi-hse-sysclk-only-div1-and","errorCode":null,"errorMessage":"Invalid ahb5_pre for HSI/HSE sysclk: only DIV1 and DIV2 are allowed","messagePattern":"Invalid ahb5_pre for HSI/HSE sysclk: only DIV1 and DIV2 are allowed","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/rcc/wba.rs","lineNumber":380,"sourceCode":"        w.set_sw(config.sys);\n    });\n    while RCC.cfgr1().read().sws() != config.sys {}\n\n    RCC.cfgr2().modify(|w| {\n        w.set_hpre(config.ahb_pre);\n        w.set_ppre1(config.apb1_pre);\n        w.set_ppre2(config.apb2_pre);\n    });\n\n    // Set AHB5 prescaler depending on sysclk source\n    RCC.cfgr4().modify(|w| match config.sys {\n        // When using HSI or HSE, use HDIV5 bit (0 = div1, 1 = div2)\n        Sysclk::Hsi | Sysclk::Hse => {\n            // Only Div1 and Div2 are valid for HDIV5, enforce this\n            match config.ahb5_pre {\n                AHB5Prescaler::Div1 => w.set_hdiv5(Hdiv5::Div1),\n                AHB5Prescaler::Div2 => w.set_hdiv5(Hdiv5::Div2),\n                _ => panic!(\"Invalid ahb5_pre for HSI/HSE sysclk: only DIV1 and DIV2 are allowed\"),\n            };\n        }\n        // When using PLL1, use HPRE5 bits [2:0]\n        Sysclk::Pll1R => {\n            w.set_hpre5(config.ahb5_pre);\n        }\n        _ => {}\n    });\n\n    let hclk5 = sys_clk / config.ahb5_pre;\n\n    #[cfg(all(stm32wba, peri_usb_otg_hs))]\n    let usb_refck = match config.mux.otghssel {\n        Otghssel::Hse => hse,\n        Otghssel::HseDiv2 => hse.map(|hse_val| hse_val / 2u8),\n        Otghssel::Pll1P => pll1.p,\n        Otghssel::Pll1PDiv2 => pll1.p.map(|pll1p_val| pll1p_val / 2u8),\n    };","sourceCodeStart":362,"sourceCodeEnd":398,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/rcc/wba.rs#L362-L398","documentation":"On STM32WBA, when the system clock source is HSI or HSE, the AHB5 prescaler can only be Div1 or Div2, implemented via the single HDIV5 bit. embassy-stm32's RCC init panics if config.ahb5_pre is set to any HPRE-style divider (Div4, Div8, ...) in this configuration, since the hardware has no encoding for it.","triggerScenarios":"rcc init with config.sysclk = Sysclk::Hsi or Sysclk::Hse and config.ahb5_pre = AHB5Prescaler::Div4 (or any divider other than Div1/Div2).","commonSituations":"Copying an AHB5 prescaler value from a PLL1R-based config and then switching sysclk to HSI/HSE; wanting a large AHB5 divide from the raw oscillator, which the hardware simply does not support.","solutions":["Set config.ahb5_pre to AHB5Prescaler::Div1 or AHB5Prescaler::Div2 while using HSI/HSE sysclk","If you need deeper AHB5 division, switch sysclk to Sysclk::Pll1R so the full HPRE5 bits are used","Pre-divide via PLL1 (feed HSI/HSE through PLL1 with a suitable divider) and clock from PLL1R instead"],"exampleFix":"// before\nconfig.sysclk = Some(Sysclk::Hsi);\nconfig.ahb5_pre = AHB5Prescaler::Div4; // panic\n// after\nconfig.sysclk = Some(Sysclk::Hsi);\nconfig.ahb5_pre = AHB5Prescaler::Div1; // or Div2 only","handlingStrategy":"validation","validationCode":"if matches!(config.sysclk, Some(Sysclk::Hsi) | Some(Sysclk::Hse)) {\n    assert!(matches!(config.ahb5_pre, AHB5Prescaler::Div1 | AHB5Prescaler::Div2),\n        \"HSI/HSE sysclk allows only Div1/Div2 for AHB5\");\n}","typeGuard":"fn ahb5_pre_valid_for_hsi_hse(pre: &AHB5Prescaler) -> bool {\n    matches!(pre, AHB5Prescaler::Div1 | AHB5Prescaler::Div2)\n}","tryCatchPattern":null,"preventionTips":["When switching sysclk source, re-check ahb5_pre constraints for the new source","Use Div1/Div2 with HSI/HSE; deep dividers require PLL1R sysclk","Update ahb5_pre whenever porting configs between sysclk sources","Read the WBA RCC chapter on HDIV5 vs HPRE5 encodings"],"tags":["rust","embedded","stm32","wba","rcc","clock-config"],"backgroundTag":"invalid-enum-value","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}