{"record":{"id":"b7974a7edeab127d","repo":"embassy-rs/embassy","slug":"ic1-is-not-ready-to-be-selected-as-cpu-clock-sourc","errorCode":null,"errorMessage":"IC1 is not ready to be selected as CPU clock source","messagePattern":"IC1 is not ready to be selected as CPU clock source","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/rcc/n6.rs","lineNumber":358,"sourceCode":"            debug!(\"  - APB4\");\n            w.set_ppre4(config.apb4);\n        }\n        if config.apb5 > w.ppre5() {\n            debug!(\"  - APB5\");\n            w.set_ppre5(config.apb5);\n        }\n        if config.ahb > w.hpre() {\n            debug!(\"  - AHB\");\n            w.set_hpre(config.ahb);\n        }\n    });\n    // cpuclk\n    debug!(\"configuring cpuclk\");\n    match config.cpu {\n        CpuClk::Hsi if !RCC.sr().read().hsirdy() => panic!(\"HSI is not ready to be selected as CPU clock source\"),\n        CpuClk::Msi if !RCC.sr().read().msirdy() => panic!(\"MSI is not ready to be selected as CPU clock source\"),\n        CpuClk::Hse if !RCC.sr().read().hserdy() => panic!(\"HSE is not ready to be selected as CPU clock source\"),\n        CpuClk::Ic1 if !ic_enabled(1) => panic!(\"IC1 is not ready to be selected as CPU clock source\"),\n        _ => {}\n    }\n    // set source\n    let cpusw = Cpusw::from_bits(config.cpu.to_bits());\n    RCC.cfgr().modify(|w| w.set_cpusw(cpusw));\n    // wait for changes to take effect\n    while RCC.cfgr().read().cpusws() != Cpusws::from_bits(config.cpu.to_bits()) {}\n\n    // sysclk\n    debug!(\"configuring sysclk\");\n    match config.sys {\n        SysClk::Hsi if !RCC.sr().read().hsirdy() => panic!(\"HSI is not ready to be selected as system clock source\"),\n        SysClk::Msi if !RCC.sr().read().msirdy() => panic!(\"MSI is not ready to be selected as system clock source\"),\n        SysClk::Hse if !RCC.sr().read().hserdy() => panic!(\"HSE is not ready to be selected as system clock source\"),\n        SysClk::Ic2 if !ic_enabled(2) || !ic_enabled(6) || !ic_enabled(11) => panic!(\n            \"IC2 is not ready to be selected as system clock source (make sure that IC6 and IC11 were configured as well)\"\n        ),\n        _ => {}","sourceCodeStart":340,"sourceCodeEnd":376,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/rcc/n6.rs#L340-L376","documentation":"On STM32N6, IC1 can be selected as the CPU clock source, but only if it was enabled. Before the switch, the code checks `ic_enabled(1)`; if IC1 was never configured, its output doesn't exist and the library panics instead of switching to a dead clock.","triggerScenarios":"Setting `config.cpu = CpuClk::Ic1` while no IC1 entry is configured/enabled in `config.ics` — IC1 omitted, set to None, or its source PLL not enabled.","commonSituations":"Selecting Ic1 as cpu clock but forgetting the `ics[0]` entry; IC1 configured against a PLL that isn't enabled so it stays disabled; copy-pasted config missing IC definitions.","solutions":["Configure IC1 in the rcc config with a ready source, e.g. `ics: [Some(Ic { source: IcSource::Pll1, ..Default::default() }), ..]`, and enable the referenced PLL.","Or select a directly-ready CPU source (Hsi/Hse/Msi) in `config.cpu`.","Ensure IC1's source oscillator/PLL is ready before init (check its ready flags path)."],"exampleFix":"// before\nrcc: RccConfig { cpu: CpuClk::Ic1, ..Default::default() }, // ic1 not configured\n// after\nrcc: RccConfig {\n    cpu: CpuClk::Ic1,\n    ics: [Some(Ic { source: IcSource::Pll1, div: IcDiv::DIV1 }), ..Default::default()],\n    ..Default::default()\n},","handlingStrategy":"validation","validationCode":"if config.rcc.cpu == CpuClk::Ic1 && config.rcc.ics.get(0).map_or(true, |ic| ic.is_none()) {\n    panic!(\"CpuClk::Ic1 requires IC1 to be configured in rcc.ics\");\n}","typeGuard":"fn ic1_configured(rcc: &RccConfig) -> bool {\n    rcc.cpu != CpuClk::Ic1 || rcc.ics.first().map_or(false, |ic| ic.is_some())\n}","tryCatchPattern":null,"preventionTips":["Configure IC1 (with an enabled source PLL) whenever CpuClk::Ic1 is selected.","Remember IC1 depends on its upstream PLL being ready, not just the IC entry.","Validate the full cpu/sys/ics config at compile time in board config builders where possible."],"tags":["rust","embedded","rcc","stm32n6","ic1","panic"],"backgroundTag":"invalid-state-transition","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}