{"record":{"id":"ba9b8d6d4ae56c9c","repo":"embassy-rs/embassy","slug":"usb-hs-phy-reference-clock-should-be-19-2-20-or-2","errorCode":null,"errorMessage":"USB HS PHY reference clock should be 19.2, 20 or 24 MHz but is {} Hz. Please double-check your RCC settings.","messagePattern":"USB HS PHY reference clock should be 19\\.2, 20 or 24 MHz but is (.+?) Hz\\. Please double-check your RCC settings\\.","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/usb/otg.rs","lineNumber":507,"sourceCode":"    ///\n    /// Called by `common_init` before the OTG core is enabled and reset. Empty for every\n    /// family whose PHY is handled by the core's own clock/power gating.\n    fn phy_init() {}\n}\n\n/// STM32N6: map the PHY reference clock to `USBPHYC_CR.FSEL`.\n///\n/// The integrated High-Speed PHY only accepts these three frequencies\n/// (RM0486 Rev 4, `USBPHYC_CR.FSEL`, p. 3929).\n#[cfg(stm32n6)]\npub(super) fn fsel_from_freq(freq: crate::time::Hertz) -> crate::pac::usbphyc::vals::Fsel {\n    use crate::pac::usbphyc::vals::Fsel;\n\n    match freq.0 {\n        19_200_000 => Fsel::Mhz192,\n        20_000_000 => Fsel::Mhz20,\n        24_000_000 => Fsel::Mhz24,\n        _ => panic!(\n            \"USB HS PHY reference clock should be 19.2, 20 or 24 MHz but is {} Hz. Please double-check your RCC settings.\",\n            freq.0\n        ),\n    }\n}\n\n/// USB instance trait.\n#[allow(private_bounds)]\npub trait Instance: SealedInstance + PeripheralType + RccPeripheral + 'static {\n    /// Interrupt for this USB instance.\n    type Interrupt: interrupt::typelevel::Interrupt;\n}\n\n// Internal PHY pins\npin_trait!(DpPin, Instance);\npin_trait!(DmPin, Instance);\n\n// External PHY pins","sourceCodeStart":489,"sourceCodeEnd":525,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/usb/otg.rs#L489-L525","documentation":"fsel_from_freq maps the USBPHYC reference clock to the Fsel register value; the PHY PLL only accepts 19.2, 20, or 24 MHz as selectable inputs. If common_init reaches this mapping with any other frequency, there is no valid Fsel encoding, so the library panics rather than misconfiguring the PHY.","triggerScenarios":"On parts whose OTG_HS goes through the internal USBPHYC, calling fsel_from_freq (via USB driver common_init) with a PHY reference clock outside {19.2, 20, 24} MHz.","commonSituations":"RCC configurations that feed the USBPHYC 16/26/32 MHz (legal for some other check but not for Fsel), or a generic 48 MHz USB clock routed to the PHY; mixing clock-tree examples across chip families.","solutions":["Set the RCC so the USBPHYC reference clock is exactly 19.2, 20, or 24 MHz (usually via PLL3 with appropriate dividers, per the ST reference manual for your part)","Cross-check against the chip-specific clock-tree example in embassy-stm32 examples/ for your board","If you need OTG_HS, do not reuse a 48 MHz FS clock tree; the HS PHY needs one of the three listed reference frequencies"],"exampleFix":"// before\nconfig.pll3.divp/divq -> usbphyc_ck = 32_000_000;\n// after\nconfig.pll3.divp/divq -> usbphyc_ck = 24_000_000; // maps to Fsel::Mhz24","handlingStrategy":"validation","validationCode":"let freq = <periph>::frequency();\nassert!(matches!(freq.0, 19_200_000 | 20_000_000 | 24_000_000), \"USBPHYC ref {} Hz not 19.2/20/24 MHz\", freq.0);","typeGuard":"fn phy_ref_ok(hz: u32) -> bool { matches!(hz, 19_200_000 | 20_000_000 | 24_000_000) }","tryCatchPattern":null,"preventionTips":["Configure PLL3 (or the PHY ref mux) to one of 19.2/20/24 MHz for OTG_HS","Do not reuse a 48 MHz FS clock tree for the HS PHY","Check the ST reference manual's USBPHYC fsel table when choosing dividers"],"tags":["embedded","stm32","usb","hs-phy","clock-config","panic"],"backgroundTag":"invalid-config-value","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}