{"record":{"id":"bfccd32059b77a55","repo":"dotnet/runtime","slug":"cpu-doesn-t-seem-to-support-any-vectorized-isa-by","errorCode":null,"errorMessage":"CPU doesn't seem to support any vectorized ISA, bye-bye\n","messagePattern":"CPU doesn't seem to support any vectorized ISA, bye-bye\n","errorType":"console","errorClass":null,"httpStatus":null,"severity":"error","filePath":"src/coreclr/gc/vxsort/standalone/demo/demo.cpp","lineNumber":76,"sourceCode":"    }\n    else if (IsSupportedInstructionSet (InstructionSet::AVX512F))\n    {\n        fprintf(stderr, \"Sorting with AVX512...\");\n        do_vxsort_avx512(begin, end, range_low, range_high);\n        fprintf(stderr, \"...done!\\n\");\n    }\n    else\n#elif defined(CPU_FEATURES_ARCH_AARCH64)\n    if (IsSupportedInstructionSet (InstructionSet::NEON))\n    {\n        fprintf(stderr, \"Sorting with NEON...\");\n        do_vxsort_neon(begin, end, range_low, range_high);\n        fprintf(stderr, \"...done!\\n\");\n    }\n    else\n#endif\n    {\n        fprintf(stderr, \"CPU doesn't seem to support any vectorized ISA, bye-bye\\n\");\n        return -2;\n    }\n\n    auto prev = START - (1 << SHIFT);\n    for (auto & element : v) {\n        fprintf(stderr, \"%p\\n\", element);\n        assert(element == prev + (1 << SHIFT));\n        prev = element;\n    }\n\n    return 0;\n}\n","sourceCodeStart":58,"sourceCodeEnd":89,"githubUrl":"https://github.com/dotnet/runtime/blob/290d5ab72cc1102813fbc0406fb186ceadabc340/src/coreclr/gc/vxsort/standalone/demo/demo.cpp#L58-L89","documentation":"After InitSupportedInstructionSet, the vxsort demo (demo.cpp:74-77) checks for AVX2, then AVX512F on x86 (NEON on AArch64). If none of the supported vectorized ISAs are present, it falls into the else block, prints this, and returns -2. The CPU cannot run the vectorized sort kernels.","triggerScenarios":"Running the x86 demo on a CPU without AVX2 and AVX512F; running on a VM that hides AVX support; an older Intel/AMD CPU; an AArch64 core without NEON (rare).","commonSituations":"Benchmarking on a legacy/Atom CPU; a cloud VM with a restricted CPU feature set; running under an emulator lacking AVX.","solutions":["Run on a host whose CPU supports AVX2 (most Intel Haswell+/AMD Ryzen and later) or NEON.","Expose AVX to the VM (check hypervisor CPU flag passthrough).","If only testing, use a different sort path / do not rely on this demo."],"exampleFix":"// before (VM hides AVX)\n./demo 1000000   # CPU doesn't seem to support any vectorized ISA, bye-bye\n// after (enable AVX2 passthrough in hypervisor)\n./demo 1000000","handlingStrategy":"validation","validationCode":"// Detect AVX2/AVX512 (x86) or NEON (ARM) before running the demo.\n#include <cpuid.h>\nunsigned int eax, ebx, ecx, edx;\n__cpuid(7, 0, eax, ebx, ecx, edx);\nbool hasAvx2 = (ebx & (1 << 5)) != 0;\nbool hasAvx512 = (ebx & (1 << 16)) != 0;\nif (!(hasAvx2 || hasAvx512)) { fprintf(stderr, \"no vectorized ISA; aborting\\n\"); return EXIT_FAILURE; }","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Run vectorized benchmarks only on AVX2+/NEON hardware.","Expose AVX to VMs via CPU-flag passthrough.","Skip the demo in CI on CPUs lacking the required ISA."],"tags":["vxsort","demo","cpu","avx2","neon","hardware"],"analyzedSha":"290d5ab72cc1102813fbc0406fb186ceadabc340","analyzedAt":"2026-08-06T19:57:01.276Z","schemaVersion":2},"datasetVersion":"2026-08-06T23:17:07.152Z"}