{"record":{"id":"c485f9db5b2c92c8","repo":"embassy-rs/embassy","slug":"invalid-hclk-frequency-should-be-at-least-25-mhz","errorCode":null,"errorMessage":"Invalid HCLK frequency - should be at least 25 MHz.","messagePattern":"Invalid HCLK frequency - should be at least 25 MHz\\.","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/eth/sma/v1.rs","lineNumber":46,"sourceCode":"        critical_section::with(|_| {\n            #[cfg(eth_v1a)]\n            let reg = crate::pac::RCC.ahbenr();\n\n            #[cfg(any(eth_v1b, eth_v1c))]\n            let reg = crate::pac::RCC.ahb1enr();\n\n            reg.modify(|w| {\n                w.set_ethen(true);\n            })\n        });\n\n        let hclk = unsafe { crate::rcc::get_freqs().hclk1.to_hertz() };\n        let hclk = unwrap!(hclk, \"SMA requires HCLK to be enabled, but it was not.\");\n        let hclk_mhz = hclk.0 / 1_000_000;\n\n        // Set the MDC clock frequency in the range 1MHz - 2.5MHz\n        let clock_range = match hclk_mhz {\n            0..=24 => panic!(\"Invalid HCLK frequency - should be at least 25 MHz.\"),\n            25..=34 => Cr::Cr2035,     // Divide by 16\n            35..=59 => Cr::Cr3560,     // Divide by 26\n            60..=99 => Cr::Cr60100,    // Divide by 42\n            100..=149 => Cr::Cr100150, // Divide by 62\n            150..=216 => Cr::Cr150168, // Divide by 102\n            _ => {\n                panic!(\"HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider\")\n            }\n        };\n\n        Self {\n            _peri: peri,\n            clock_range,\n            _pins: [\n                new_pin!(mdio, AfType::output(OutputType::PushPull, Speed::VeryHigh)).unwrap(),\n                new_pin!(mdc, AfType::output(OutputType::PushPull, Speed::VeryHigh)).unwrap(),\n            ],\n        }","sourceCodeStart":28,"sourceCodeEnd":64,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/eth/sma/v1.rs#L28-L64","documentation":"The v1 Ethernet Station Management block derives MDC from HCLK. To keep MDC in the 1–2.5 MHz window, HCLK must be at least 25 MHz so the smallest divider is valid; below that no clock-range value exists and the driver panics.","triggerScenarios":"Constructing the v1 StationManagement while rcc hclk1 is < 25 MHz (hclk_mhz in 0..=24).","commonSituations":"Low-power/HSI-only clock configs; hclk1 unassigned or very small; early bring-up before RCC is fully configured.","solutions":["Raise HCLK1 to at least 25 MHz in the RCC config before creating the Ethernet driver.","Verify rcc::get_freqs().hclk1 is nonzero and correct after RCC init.","Use a board RCC default meeting Ethernet clocking requirements."],"exampleFix":"// before\nconfig.sys = Sysclk::HSI; // ~16 MHz\n// after\nconfig.sys = Sysclk::PLL1_R; // 80 MHz PLL -> hclk >= 25 MHz","handlingStrategy":"validation","validationCode":"let hclk = embassy_stm32::rcc::get_freqs().hclk1.0;\nassert!(hclk >= 25_000_000, \"Ethernet requires HCLK1 >= 25 MHz, got {}\", hclk);","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Size the RCC PLL so HCLK1 >= 25 MHz whenever Ethernet is used.","Check get_freqs().hclk1 right after RCC init."],"tags":["embedded","rust","ethernet","clock-config","stm32"],"backgroundTag":"value-out-of-range","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}