{"record":{"id":"c67c9ecbfea96e0a","repo":"wasmerio/wasmer","slug":"x86-support-requires-sse2","errorCode":null,"errorMessage":"x86 support requires SSE2","messagePattern":"x86 support requires SSE2","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"lib/compiler-cranelift/src/config.rs","lineNumber":193,"sourceCode":"        self\n    }\n\n    /// The optimization levels when optimizing the IR.\n    pub fn opt_level(&mut self, opt_level: CraneliftOptLevel) -> &mut Self {\n        self.opt_level = opt_level;\n        self\n    }\n\n    /// Generates the ISA for the provided target\n    pub fn isa(&self, target: &Target) -> CodegenResult<Arc<dyn TargetIsa>> {\n        let mut builder =\n            lookup(target.triple().clone()).expect(\"construct Cranelift ISA for triple\");\n        // Cpu Features\n        let cpu_features = target.cpu_features();\n        if target.triple().architecture == Architecture::X86_64\n            && !cpu_features.contains(CpuFeature::SSE2)\n        {\n            panic!(\"x86 support requires SSE2\");\n        }\n        if cpu_features.contains(CpuFeature::SSE3) {\n            builder.enable(\"has_sse3\").expect(\"should be valid flag\");\n        }\n        if cpu_features.contains(CpuFeature::SSSE3) {\n            builder.enable(\"has_ssse3\").expect(\"should be valid flag\");\n        }\n        if cpu_features.contains(CpuFeature::SSE41) {\n            builder.enable(\"has_sse41\").expect(\"should be valid flag\");\n        }\n        if cpu_features.contains(CpuFeature::SSE42) {\n            builder.enable(\"has_sse42\").expect(\"should be valid flag\");\n        }\n        if cpu_features.contains(CpuFeature::POPCNT) {\n            builder.enable(\"has_popcnt\").expect(\"should be valid flag\");\n        }\n        if cpu_features.contains(CpuFeature::AVX) {\n            builder.enable(\"has_avx\").expect(\"should be valid flag\");","sourceCodeStart":175,"sourceCodeEnd":211,"githubUrl":"https://github.com/wasmerio/wasmer/blob/8c4b9ee9d33fb2068863fbb3d328683e7e6ff7f5/lib/compiler-cranelift/src/config.rs#L175-L211","documentation":"CraneliftCompiler::isa builds the target ISA description for compilation. On X86_64 targets the code requires the SSE2 CPU feature — it is the baseline for 64-bit x86 backend support — and panics if the target's CPU feature set lacks it. This guarantees the generated code meets the x86-64 baseline ISA.","triggerScenarios":"Calling isa() (during compiler construction / module compilation) with a target whose declared cpu_features do not include SSE2 — typically after building a custom Target with manually cleared/omitted features rather than from native CPU detection.","commonSituations":"Constructing a cross-compilation Target programmatically and forgetting to add CpuFeature::SSE2; targeting emulators/qemu CPU models that mask SSE2; custom engine configs supplying an explicit target triple + feature set that omits baseline features.","solutions":["Add CpuFeature::SSE2 to the target's cpu_features when constructing a custom x86_64 Target.","Use target detection from the host (Cpu::for_native / Target::new default) instead of hand-built feature sets.","If deliberately targeting non-SSE2 x86, that is unsupported — switch to a supported baseline or a different architecture.","Verify with lscpu / cpuinfo that the execution environment actually reports SSE2."],"exampleFix":"// before\nlet mut target = Target::new(triple, cpu_features_without_sse2);\n// after\nlet mut cpu_features = EnumSet::new();\ncpu_features.insert(CpuFeature::SSE2); // required baseline for x86_64\nlet target = Target::new(triple, cpu_features);","handlingStrategy":"validation","validationCode":"use wasmer_compiler::{CpuFeature, Target, Triple};\nuse enumset::EnumSet;\nfn assert_x86_64_baseline(triple: &Triple, feats: &EnumSet<CpuFeature>) {\n    if triple.architecture == target_lexicon::Architecture::X86_64\n        && !feats.contains(CpuFeature::SSE2)\n    {\n        panic!(\"custom x86_64 target must include CpuFeature::SSE2\");\n    }\n}","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Always include SSE2 when hand-building x86_64 Targets.","Prefer native CPU detection over manual feature sets.","Verify target CPU models in emulators report baseline x86-64 features."],"tags":["rust","panic","cranelift","cpu-features","x86","target"],"backgroundTag":"missing-cpu-feature","analyzedSha":"8c4b9ee9d33fb2068863fbb3d328683e7e6ff7f5","analyzedAt":"2026-09-01T23:06:31.009Z","contentChangedAt":null,"schemaVersion":2},"datasetVersion":"2026-09-09T06:17:21.866Z"}