{"record":{"id":"ca82dc6900ccc8a8","repo":"embassy-rs/embassy","slug":"hclk-results-in-mdc-clock-2-5mhz-even-for-the-hi-ca82dc","errorCode":null,"errorMessage":"HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider","messagePattern":"HCLK results in MDC clock > 2\\.5MHz even for the highest CSR clock divider","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/eth/sma/v2.rs","lineNumber":53,"sourceCode":"                w.set_eth1macen(true);\n            });\n        });\n\n        let hclk = unsafe { crate::rcc::get_freqs().hclk1.to_hertz() };\n        let hclk = unwrap!(hclk, \"SMA requires HCLK to be enabled, but it was not.\");\n        let hclk_mhz = hclk.0 / 1_000_000;\n\n        // Set the MDC clock frequency in the range 1MHz - 2.5MHz\n        #[cfg(not(eth_v2a))]\n        let clock_range = match hclk_mhz {\n            0..=34 => 2,    // Divide by 16\n            35..=59 => 3,   // Divide by 26\n            60..=99 => 0,   // Divide by 42\n            100..=149 => 1, // Divide by 62\n            150..=249 => 4, // Divide by 102\n            250..=310 => 5, // Divide by 124\n            _ => {\n                panic!(\"HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider\")\n            }\n        };\n        // The eth_v2a MAC supports two extra dividers for higher HCLK\n        // frequencies. Boundaries match the ST HAL (HAL_ETH_SetMDIOClockRange).\n        #[cfg(eth_v2a)]\n        let clock_range = match hclk_mhz {\n            0..=34 => 2,    // Divide by 16\n            35..=59 => 3,   // Divide by 26\n            60..=99 => 0,   // Divide by 42\n            100..=149 => 1, // Divide by 62\n            150..=249 => 4, // Divide by 102\n            250..=299 => 5, // Divide by 124\n            300..=499 => 6, // Divide by 204\n            _ => 7,         // Divide by 324\n        };\n\n        Self {\n            _peri: peri,","sourceCodeStart":35,"sourceCodeEnd":71,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/eth/sma/v2.rs#L35-L71","documentation":"Same family as v1: the v2 StationManagement picks an MDC CSR clock range from HCLK. If hclk_mhz exceeds 310 MHz (largest table entry, divide by 124), no valid clock range exists and the driver panics.","triggerScenarios":"Constructing the v2 StationManagement on an eth_v2 (non-v2a) part with hclk_mhz > 310.","commonSituations":"Very high HCLK RCC configs on v2 Ethernet parts; forgetting that the eth_v2a extended divider table applies only to specific MACs.","solutions":["Lower HCLK to <= 310 MHz in the RCC config.","If the target MAC is eth_v2a, ensure the cfg path is active so the extended divider table is used.","Pick the highest divider arm appropriate for the actual HCLK."],"exampleFix":"// before\nconfig.pll = Pll { freq: 400.MHz(), .. };\n// after\nconfig.pll = Pll { freq: 240.MHz(), .. }; // 150..=249 -> divide by 102","handlingStrategy":"validation","validationCode":"let hclk_mhz = embassy_stm32::rcc::get_freqs().hclk1.0 / 1_000_000;\nassert!(hclk_mhz <= 310, \"v2 Ethernet requires HCLK1 <= 310 MHz, got {} MHz\", hclk_mhz);","typeGuard":null,"tryCatchPattern":null,"preventionTips":["Cap HCLK1 at 310 MHz for eth_v2 (non-v2a) parts.","Use an eth_v2a MAC (extended dividers) if higher HCLK is required."],"tags":["embedded","rust","ethernet","clock-config","stm32"],"backgroundTag":"value-out-of-range","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}