{"record":{"id":"cc2b73692eea066b","repo":"embassy-rs/embassy","slug":"hse-is-not-ready-to-be-selected-as-system-clock-so","errorCode":null,"errorMessage":"HSE is not ready to be selected as system clock source","messagePattern":"HSE is not ready to be selected as system clock source","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/rcc/n6.rs","lineNumber":372,"sourceCode":"    match config.cpu {\n        CpuClk::Hsi if !RCC.sr().read().hsirdy() => panic!(\"HSI is not ready to be selected as CPU clock source\"),\n        CpuClk::Msi if !RCC.sr().read().msirdy() => panic!(\"MSI is not ready to be selected as CPU clock source\"),\n        CpuClk::Hse if !RCC.sr().read().hserdy() => panic!(\"HSE is not ready to be selected as CPU clock source\"),\n        CpuClk::Ic1 if !ic_enabled(1) => panic!(\"IC1 is not ready to be selected as CPU clock source\"),\n        _ => {}\n    }\n    // set source\n    let cpusw = Cpusw::from_bits(config.cpu.to_bits());\n    RCC.cfgr().modify(|w| w.set_cpusw(cpusw));\n    // wait for changes to take effect\n    while RCC.cfgr().read().cpusws() != Cpusws::from_bits(config.cpu.to_bits()) {}\n\n    // sysclk\n    debug!(\"configuring sysclk\");\n    match config.sys {\n        SysClk::Hsi if !RCC.sr().read().hsirdy() => panic!(\"HSI is not ready to be selected as system clock source\"),\n        SysClk::Msi if !RCC.sr().read().msirdy() => panic!(\"MSI is not ready to be selected as system clock source\"),\n        SysClk::Hse if !RCC.sr().read().hserdy() => panic!(\"HSE is not ready to be selected as system clock source\"),\n        SysClk::Ic2 if !ic_enabled(2) || !ic_enabled(6) || !ic_enabled(11) => panic!(\n            \"IC2 is not ready to be selected as system clock source (make sure that IC6 and IC11 were configured as well)\"\n        ),\n        _ => {}\n    }\n    // switch the system bus clock\n    let syssw = Syssw::from_bits(config.sys.to_bits());\n    RCC.cfgr().modify(|w| w.set_syssw(syssw));\n    // wait for changes to be applied\n    while RCC.cfgr().read().syssws() != Syssws::from_bits(config.sys.to_bits()) {}\n\n    // decreasing dividers\n    debug!(\"configuring decreasing pclk dividers\");\n    RCC.cfgr2().modify(|w| {\n        if config.ahb < w.hpre() {\n            debug!(\"  - AHB\");\n            w.set_hpre(config.ahb);\n        }","sourceCodeStart":354,"sourceCodeEnd":390,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/rcc/n6.rs#L354-L390","documentation":"On STM32N6, before switching the system clock to HSE, the code checks `RCC.sr().hserdy()`. If the high-speed external oscillator is not ready, selecting it as the system bus clock source would clock the bus from a dead source, so the library panics.","triggerScenarios":"Setting `config.sys = SysClk::Hse` while `hserdy()` is false — HSE never enabled in the rcc config, wrong crystal/bypass mode, or HSE hardware startup failure (bad crystal, load caps, no external clock in bypass).","commonSituations":"Boards without an HSE crystal where the config still selects HSE; bypass mode mismatched with actual clock input; HSE enabled only for PLL use but sysclk switched to HSE directly in a reinit that re-disables it.","solutions":["Configure HSE (`hse: Some(Hse { mode, freq, ... })`) so it is started and awaited ready before the switch.","If no HSE hardware exists, switch `config.sys` to Hsi, Msi, or Ic2.","Check hardware (crystal, load capacitors, external clock present if bypass) so `hserdy` can set."],"exampleFix":"// before\nrcc: RccConfig { sys: SysClk::Hse, ..Default::default() }, // hse not configured\n// after\nrcc: RccConfig {\n    hse: Some(Hse { freq: MegaHertz::new(48), mode: HseMode::Bypass }),\n    sys: SysClk::Hse,\n    ..Default::default()\n},","handlingStrategy":"validation","validationCode":"if config.rcc.sys == SysClk::Hse && config.rcc.hse.is_none() {\n    panic!(\"SysClk::Hse requires an hse config in rcc\");\n}","typeGuard":"fn hse_ready_for_sys(rcc: &RccConfig) -> bool {\n    rcc.sys != SysClk::Hse || rcc.hse.is_some()\n}","tryCatchPattern":null,"preventionTips":["Configure hse (mode + frequency) before selecting SysClk::Hse.","Verify HSE hardware (crystal, load caps, bypass clock source) on the real board.","If HSE is only intended to feed a PLL, don't also switch sysclk to HSE unless it is enabled."],"tags":["rust","embedded","rcc","stm32n6","hse","sysclk","panic"],"backgroundTag":"invalid-state-transition","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}