{"record":{"id":"cc9205fcf1a13715","repo":"wasmerio/wasmer","slug":"unsupported-location","errorCode":null,"errorMessage":"unsupported location","messagePattern":"unsupported location","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"lib/compiler-singlepass/src/machine_riscv.rs","lineNumber":201,"sourceCode":"                if imm == 0 {\n                    Ok(Location::GPR(GPR::XZero))\n                } else if allow_imm.compatible_imm(imm) {\n                    Ok(src)\n                } else {\n                    let tmp = if let Some(wanted) = wanted {\n                        wanted\n                    } else {\n                        let tmp = self.acquire_temp_gpr().ok_or_else(|| {\n                            CompileError::Codegen(\"singlepass cannot acquire temp gpr\".to_owned())\n                        })?;\n                        temps.push(tmp);\n                        tmp\n                    };\n                    self.assembler.emit_mov_imm(Location::GPR(tmp), imm as _)?;\n                    Ok(Location::GPR(tmp))\n                }\n            }\n            _ => todo!(\"unsupported location\"),\n        }\n    }\n\n    fn location_to_fpr(\n        &mut self,\n        sz: Size,\n        src: Location,\n        temps: &mut Vec<FPR>,\n        allow_imm: ImmType,\n        read_val: bool,\n    ) -> Result<Location, CompileError> {\n        match src {\n            Location::SIMD(_) => Ok(src),\n            Location::GPR(_) => {\n                let tmp = self.acquire_temp_simd().ok_or_else(|| {\n                    CompileError::Codegen(\"singlepass cannot acquire temp fpr\".to_owned())\n                })?;\n                temps.push(tmp);","sourceCodeStart":183,"sourceCodeEnd":219,"githubUrl":"https://github.com/wasmerio/wasmer/blob/8c4b9ee9d33fb2068863fbb3d328683e7e6ff7f5/lib/compiler-singlepass/src/machine_riscv.rs#L183-L219","documentation":"`location_to_reg` in the RISC-V machine backend converts a compile-time `Location` (GPR/FPR/stack slot/etc.) to a register; the `_ => todo!(\"unsupported location\")` arm panics when it receives a location kind the RISC-V backend cannot materialize (e.g. certain immediate or pseudo locations). Called from FPR conversion and relaxed binop/atomic/cmp emission helpers.","triggerScenarios":"Singlepass RISC-V code generation where an operand location is not a GPR/FPR the backend expects — e.g. an immediate or unsupported location passed to emit_relaxed_binop / emit_relaxed_binop3 / emit_relaxed_atomic_binop3 / emit_relaxed_atomic_cmpxchg / emit_relaxed_cmp via location_to_reg or location_to_fpr (machine_riscv.rs:201).","commonSituations":"Compiling wasm with instruction patterns the incomplete RISC-V singlepass backend hasn't modeled (atomics, unusual operand orders), exposing unhandled Location variants.","solutions":["Use the Cranelift backend instead of singlepass on RISC-V","Adjust/restructure the wasm module (e.g. avoid atomic ops) to steer clear of the unsupported code path","Upgrade wasmtime so RISC-V location handling covers the missing Location variants","Capture a backtrace to identify which emission helper received the bad location and file an upstream issue"],"exampleFix":"// before: singlepass on riscv with such patterns panics\nconfig.strategy(Strategy::Winch);\n// after: use the mature backend\nconfig.strategy(Strategy::Cranelift);","handlingStrategy":"fallback","validationCode":"// Prefer a backend with complete RISC-V location handling before compiling.\nlet mut config = Config::new();\nif cfg!(target_arch = \"riscv64\") {\n    config.strategy(wasmtime::Strategy::Cranelift);\n}\nlet engine = Engine::new(&config)?;","typeGuard":null,"tryCatchPattern":"let compiled = std::panic::catch_unwind(|| Module::new(&engine, &wasm_bytes));\nif compiled.is_err() {\n    // singlepass riscv hit an unsupported Location; retry with Cranelift\n    let mut cfg = Config::new();\n    cfg.strategy(Strategy::Cranelift);\n    Module::new(&Engine::new(&cfg)?, &wasm_bytes)?;\n}","preventionTips":["Use Cranelift for workloads using atomics or complex operand patterns on RISC-V","Keep wasmtime updated; RISC-V singlepass is incomplete","Add compile smoke tests per platform to catch panics before production"],"tags":["wasmtime","singlepass","riscv","codegen","panic"],"backgroundTag":"unimplemented-backend-feature","analyzedSha":"8c4b9ee9d33fb2068863fbb3d328683e7e6ff7f5","analyzedAt":"2026-09-01T23:06:31.009Z","contentChangedAt":null,"schemaVersion":2},"datasetVersion":"2026-09-09T06:17:21.866Z"}