{"record":{"id":"ccaf752d8f2d75ba","repo":"embassy-rs/embassy","slug":"dma-error-on-bdma-08x-channel","errorCode":null,"errorMessage":"DMA: error on BDMA@{:08x} channel {}","messagePattern":"DMA: error on BDMA@(.+?) channel (.+?)","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"critical","filePath":"embassy-stm32/src/dma/dma_bdma.rs","lineNumber":52,"sourceCode":"            }\n            if isr.tcif(info.num % 4) && cr.read().tcie() {\n                // Acknowledge transfer complete interrupt\n                r.ifcr(info.num / 4).write(|w| w.set_tcif(info.num % 4, true));\n                state.complete_count.fetch_add(1, Ordering::Release);\n                activity = true;\n            }\n            if !activity {\n                return;\n            }\n            state.waker.wake();\n        }\n        #[cfg(bdma)]\n        DmaInfo::Bdma(r) => {\n            let isr = r.isr().read();\n            let cr = r.ch(info.num).cr();\n\n            if isr.teif(info.num) {\n                panic!(\"DMA: error on BDMA@{:08x} channel {}\", r.as_ptr() as u32, info.num);\n            }\n\n            let mut activity = false;\n            if isr.htif(info.num) && cr.read().htie() {\n                // Acknowledge half transfer complete interrupt\n                r.ifcr().write(|w| w.set_htif(info.num, true));\n                activity = true;\n            }\n            if isr.tcif(info.num) && cr.read().tcie() {\n                // Acknowledge transfer complete interrupt\n                r.ifcr().write(|w| w.set_tcif(info.num, true));\n                #[cfg(not(armv6m))]\n                state.complete_count.fetch_add(1, Ordering::Release);\n                #[cfg(armv6m)]\n                critical_section::with(|_| {\n                    let x = state.complete_count.load(Ordering::Relaxed);\n                    state.complete_count.store(x + 1, Ordering::Release);\n                });","sourceCodeStart":34,"sourceCodeEnd":70,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/dma/dma_bdma.rs#L34-L70","documentation":"Analogous to the DMA transfer-error panic, but for the BDMA controller (used on e.g. STM32L4/G0/L5 for limited peripherals like LPUART/DAC). When the channel's transfer-error flag (teif) is observed in the BDMA interrupt, the driver panics, reporting the BDMA base address and channel number.","triggerScenarios":"on_irq servicing a BDMA channel sees isr.teif(info.num) set — invalid memory address for the BDMA (which can only access certain RAM regions), bad memory increment/size settings, or a peripheral error on a BDMA-driven channel.","commonSituations":"Buffer placed in memory region BDMA cannot reach (BDMA often only accesses SRAM1/SRAM2 at fixed addresses); wrong channel configuration for LPUART/DAC; transfer size larger than the 65535 max for BDMA; buffer freed before completion.","solutions":["Place the buffer in a BDMA-accessible RAM region (check the reference manual's BDMA memory map limits; use a linker section if needed).","Verify channel configuration: memory/peripheral size, increment mode, and direction match the peripheral.","Check the transfer length is within BDMA's 16-bit CNDTR limit.","Keep the buffer valid for the entire transfer and check peripheral-level error flags too."],"exampleFix":"// before\n#[link_section = \".axisram\"]\nstatic BUF: [u8; 64] = [0u8; 64]; // region not reachable by BDMA\n\n// after\n#[link_section = \".sram1\"]\nstatic BUF: [u8; 64] = [0u8; 64]; // BDMA-accessible region","handlingStrategy":"validation","validationCode":"// BDMA can only access specific SRAM regions; check before use:\nlet addr = buf.as_ptr() as u32;\nassert!((0x2000_0000..0x2000_c000).contains(&addr), \"buffer not in BDMA-accessible SRAM\");\nassert!(len <= 0xFFFF, \"BDMA CNDTR is 16-bit, transfer too large\");","typeGuard":"fn bdma_accessible<T>(buf: &[T]) -> bool {\n    let addr = buf.as_ptr() as u32;\n    // Adjust range to the specific chip's BDMA-capable memory map\n    (0x2000_0000..0x2000_c000).contains(&addr)\n}","tryCatchPattern":"// Panic in IRQ: not catchable. Prevent by validating placement before transfer:\nassert!(bdma_accessible(&buf), \"BDMA cannot reach this memory region\");","preventionTips":["Place BDMA buffers in the exact RAM region documented for BDMA access (often a fixed SRAM bank).","Keep transfer counts at or below 65535 (16-bit CNDTR).","Double-check channel configuration (size, increment, direction) against the peripheral's requirements.","Hold the buffer alive for the whole transfer with proper lifetimes or statics."],"tags":["embedded","dma","bdma","panic","interrupt"],"backgroundTag":"invalid-config-value","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}