{"record":{"id":"df1b426fbbc06218","repo":"embassy-rs/embassy","slug":"aps6404l-psram-verification-not-implemented-for-ri","errorCode":null,"errorMessage":"APS6404L PSRAM verification not implemented for RISC-V","messagePattern":"APS6404L PSRAM verification not implemented for RISC-V","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-rp/src/psram.rs","lineNumber":437,"sourceCode":"        \"movs {temp}, #0\",\n        \"str {temp}, [{qmi_base}]\",\n\n        // Memory barriers\n        \"dmb\",\n        \"dsb\",\n        \"isb\",\n        qmi_base = in(reg) qmi_base,\n        temp = out(reg) _,\n        counter = out(reg) _,\n        kgd = out(reg) kgd,\n        eid = out(reg) eid,\n        reset_enable_cmd = const RESET_ENABLE_CMD as u32,\n        read_id_cmd = const READ_ID_CMD as u32,\n        options(nostack),\n        );\n\n        #[cfg(target_arch = \"riscv32\")]\n        unimplemented!(\"APS6404L PSRAM verification not implemented for RISC-V\");\n\n        (kgd, eid)\n    }\n\n    /// Initialize PSRAM with proper timing.\n    #[unsafe(link_section = \".data.ram_func\")]\n    #[inline(never)]\n    fn init_psram(qmi: &pac::qmi::Qmi, xip_ctrl: &pac::xip_ctrl::XipCtrl, config: &Config) -> Result<(), Error> {\n        // Set PSRAM timing for APS6404\n        //\n        // Using an rxdelay equal to the divisor isn't enough when running the APS6404 close to 133 MHz.\n        // So: don't allow running at divisor 1 above 100 MHz (because delay of 2 would be too late),\n        // and add an extra 1 to the rxdelay if the divided clock is > 100 MHz (i.e., sys clock > 200 MHz).\n        let clock_hz = config.clock_hz;\n        let max_psram_freq = config.max_mem_freq;\n\n        let mut divisor: u32 = (clock_hz + max_psram_freq - 1) / max_psram_freq;\n        if divisor == 1 && clock_hz > 100_000_000 {","sourceCodeStart":419,"sourceCodeEnd":455,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-rp/src/psram.rs#L419-L455","documentation":"read_aps6404l_kgd_eid performs PIO-based reading of the APS6404L PSRAM manufacturer/device ID; the assembly path exists for ARM Cortex-M0+, but on riscv32 targets it is unconditionally unimplemented. The function therefore always panics when compiled for RISC-V RP2350 boards.","triggerScenarios":"Calling psram init/verification code (read_aps6404l_kgd_eid) on embassy-rp with target_arch = \"riscv32\" (RP2350 RISC-V core).","commonSituations":"Using the RISC-V (Hazard3) cores of the RP2350 with external PSRAM; the same code works when building for the ARM cores.","solutions":["Build for the Cortex-M33 target instead of riscv32 (e.g. thumbv8m.main-none-eabihf)","Skip or gate PSRAM verification on RISC-V and implement your own ID read via QMI direct commands","Contribute an riscv32 PIO/asm implementation for the KGD/EID read","Patch the cfg to return a known-good fallback on riscv32 if verification is not essential"],"exampleFix":"// before\n# cargo build --target riscv32imac-unknown-none-elf\n// after\n# cargo build --target thumbv8m.main-none-eabihf","handlingStrategy":"type-guard","validationCode":"#[cfg(target_arch = \"riscv32\")] compile_error!(\"PSRAM verification unsupported on riscv32; build for ARM\");","typeGuard":"const PSRAM_VERIFICATION_SUPPORTED: bool = cfg!(not(target_arch = \"riscv32\"));","tryCatchPattern":null,"preventionTips":["Build RP2350 PSRAM apps for thumbv8m.main-none-eabihf","Gate PSRAM usage behind target_arch checks in your board support crate"],"tags":["rust","embedded","riscv","psram","unimplemented"],"backgroundTag":"unsupported-platform","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}