{"record":{"id":"ecc52ea41ac1b746","repo":"embassy-rs/embassy","slug":"hsi-is-not-ready-to-be-selected-as-system-clock-so","errorCode":null,"errorMessage":"HSI is not ready to be selected as system clock source","messagePattern":"HSI is not ready to be selected as system clock source","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-stm32/src/rcc/n6.rs","lineNumber":370,"sourceCode":"    // cpuclk\n    debug!(\"configuring cpuclk\");\n    match config.cpu {\n        CpuClk::Hsi if !RCC.sr().read().hsirdy() => panic!(\"HSI is not ready to be selected as CPU clock source\"),\n        CpuClk::Msi if !RCC.sr().read().msirdy() => panic!(\"MSI is not ready to be selected as CPU clock source\"),\n        CpuClk::Hse if !RCC.sr().read().hserdy() => panic!(\"HSE is not ready to be selected as CPU clock source\"),\n        CpuClk::Ic1 if !ic_enabled(1) => panic!(\"IC1 is not ready to be selected as CPU clock source\"),\n        _ => {}\n    }\n    // set source\n    let cpusw = Cpusw::from_bits(config.cpu.to_bits());\n    RCC.cfgr().modify(|w| w.set_cpusw(cpusw));\n    // wait for changes to take effect\n    while RCC.cfgr().read().cpusws() != Cpusws::from_bits(config.cpu.to_bits()) {}\n\n    // sysclk\n    debug!(\"configuring sysclk\");\n    match config.sys {\n        SysClk::Hsi if !RCC.sr().read().hsirdy() => panic!(\"HSI is not ready to be selected as system clock source\"),\n        SysClk::Msi if !RCC.sr().read().msirdy() => panic!(\"MSI is not ready to be selected as system clock source\"),\n        SysClk::Hse if !RCC.sr().read().hserdy() => panic!(\"HSE is not ready to be selected as system clock source\"),\n        SysClk::Ic2 if !ic_enabled(2) || !ic_enabled(6) || !ic_enabled(11) => panic!(\n            \"IC2 is not ready to be selected as system clock source (make sure that IC6 and IC11 were configured as well)\"\n        ),\n        _ => {}\n    }\n    // switch the system bus clock\n    let syssw = Syssw::from_bits(config.sys.to_bits());\n    RCC.cfgr().modify(|w| w.set_syssw(syssw));\n    // wait for changes to be applied\n    while RCC.cfgr().read().syssws() != Syssws::from_bits(config.sys.to_bits()) {}\n\n    // decreasing dividers\n    debug!(\"configuring decreasing pclk dividers\");\n    RCC.cfgr2().modify(|w| {\n        if config.ahb < w.hpre() {\n            debug!(\"  - AHB\");","sourceCodeStart":352,"sourceCodeEnd":388,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-stm32/src/rcc/n6.rs#L352-L388","documentation":"During clock-tree init the requested CpuClk::Hsi source is checked against RCC's hsirdy status bit before switching cpuclk; HSI has not stabilized or was not enabled before selection, so switching the CPU clock to it would be unsafe and the guard panics. This is the HSI arm of the same readiness match that guards MSI/HSE/IC1.","triggerScenarios":"Setting `config.sys = SysClk::Hsi` while `hsirdy()` is false — HSI not enabled in the rcc config or disabled before the sysclk switch (note: the CPU-clock switch has already completed at this point).","commonSituations":"Configuring sysclk to HSI but leaving `hsi: false`; an earlier CPU-clock selection that turned HSI off; reinit flows where HSI was never re-enabled.","solutions":["Enable HSI in the rcc config (`hsi: true`) so it is ready before the sysclk switch.","Or change `config.sys` to a source that is ready (Hse/Msi/Ic2).","Review the cpu/sys config pair so both use sources that are actually enabled."],"exampleFix":"// before\nrcc: RccConfig { sys: SysClk::Hsi, ..Default::default() }, // hsi disabled\n// after\nrcc: RccConfig { hsi: true, sys: SysClk::Hsi, ..Default::default() },","handlingStrategy":"validation","validationCode":"if config.rcc.sys == SysClk::Hsi && !config.rcc.hsi {\n    panic!(\"SysClk::Hsi requires hsi: true in rcc config\");\n}","typeGuard":"fn sys_source_configured(sys: SysClk, rcc: &RccConfig) -> bool {\n    match sys {\n        SysClk::Hsi => rcc.hsi,\n        SysClk::Hse => rcc.hse.is_some(),\n        SysClk::Msi => rcc.msi.is_some(),\n        SysClk::Ic2 => rcc.ics.get(1).map_or(false, |ic| ic.is_some()),\n    }\n}","tryCatchPattern":null,"preventionTips":["Enable HSI when it is the sysclk (and possibly also the cpu) source.","Check that the cpu-clock switch step won't disable a source needed by sys.","Review config.sys and config.cpu together on every board change."],"tags":["rust","embedded","rcc","stm32n6","hsi","sysclk","panic"],"backgroundTag":"invalid-state-transition","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}