{"record":{"id":"f7ce3e632855f8e9","repo":"embassy-rs/embassy","slug":"direct-csr-command-sending-is-not-implemented-for","errorCode":null,"errorMessage":"Direct CSR command sending is not implemented for RISC-V yet","messagePattern":"Direct CSR command sending is not implemented for RISC-V yet","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-rp/src/psram.rs","lineNumber":685,"sourceCode":"        \"bne 2b\",                        // Branch if busy\n\n        // Disable Direct CSR\n        \"mov {temp}, #0\",\n        \"str {temp}, [{base}, #0]\",      // Clear DIRECT_CSR register\n\n        // Full memory barrier to ensure no prefetching\n        \"dmb\",\n        \"dsb\",\n        \"isb\",\n        base = out(reg) _,\n        temp = out(reg) _,\n        clkdiv = in(reg) config.init_clkdiv as u32,\n        enter_quad_cmd = in(reg) u32::from(init_cmd),\n        options(nostack),\n        );\n\n        #[cfg(target_arch = \"riscv32\")]\n        unimplemented!(\"Direct CSR command sending is not implemented for RISC-V yet\");\n    }\n}\n","sourceCodeStart":667,"sourceCodeEnd":688,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-rp/src/psram.rs#L667-L688","documentation":"direct_csr_send_init_command sends a direct CSR command to the PSRAM over the QMI interface using inline assembly; only the ARM path is implemented, and the riscv32 path is unconditionally unimplemented. Any direct-CSR setup on a RISC-V RP2350 build panics.","triggerScenarios":"Calling direct_csr_send_init_command during PSRAM initialization when compiled with target_arch = \"riscv32\".","commonSituations":"Initializing APS6404L PSRAM on RP2350 using the RISC-V cores instead of the ARM cores.","solutions":["Compile for the ARM (thumbv8m.main-none-eabihf) target where the asm path exists","Implement the riscv32 asm sequence mirroring the ARM version","Avoid direct CSR commands on RISC-V and configure QMI via register writes instead","Gate the CSR init behind a cfg so RISC-V builds skip it"],"exampleFix":"// before\npsram::Psram::new(p.QMI, p.PIN_0, ...); // on riscv32 target\n// after\n# build for thumbv8m.main-none-eabihf instead","handlingStrategy":"type-guard","validationCode":"#[cfg(target_arch = \"riscv32\")] compile_error!(\"direct CSR PSRAM init unsupported on riscv32\");","typeGuard":"const CSR_DIRECT_SUPPORTED: bool = cfg!(not(target_arch = \"riscv32\"));","tryCatchPattern":null,"preventionTips":["Avoid direct-CSR PSRAM init on RISC-V cores","Use ARM target builds when QMI direct commands are needed"],"tags":["rust","embedded","riscv","qmi","unimplemented"],"backgroundTag":"unsupported-platform","analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}