{"record":{"id":"fcb93d3618c9f428","repo":"embassy-rs/embassy","slug":"mclk-frequency-160-mhz-is-not-compatible-with","errorCode":null,"errorMessage":"MCLK frequency {} > 160 MHz is not compatible with the TRNG","messagePattern":"MCLK frequency (.+?) > 160 MHz is not compatible with the TRNG","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"embassy-mspm0/src/trng.rs","lineNumber":346,"sourceCode":"        });\n    }\n\n    fn power_on(&mut self) {\n        regs().gprcm().pwren().write(|w| {\n            w.set_key(PwrenKey::Key);\n            w.set_enable(true);\n        });\n    }\n\n    fn power_off(&mut self) {\n        regs().gprcm().pwren().write(|w| w.set_key(PwrenKey::Key));\n    }\n\n    fn set_div(&mut self) {\n        // L-series TRM 13.2.2: The TRNG is derived from MCLK. Datasheets specify 9.5-20 MHz range.\n        let freq = crate::sysctl::mclk_frequency();\n        let ratio = if freq > 160_000_000 {\n            panic!(\"MCLK frequency {} > 160 MHz is not compatible with the TRNG\", freq)\n        } else if freq >= 80_000_000 {\n            Ratio::DivBy8\n        } else if freq >= 60_000_000 {\n            Ratio::DivBy6\n        } else if freq >= 40_000_000 {\n            Ratio::DivBy4\n        } else if freq >= 20_000_000 {\n            Ratio::DivBy2\n        } else if freq >= 9_500_000 {\n            Ratio::DivBy1\n        } else {\n            panic!(\"MCLK frequency {} < 9.5 MHz is not compatible with the TRNG\", freq)\n        };\n        regs().clkdiv().write(|w| w.set_ratio(ratio));\n    }\n\n    fn set_decim_rate(&mut self) {\n        regs().ctl().modify(|w| w.set_decim_rate(self.decim_rate));","sourceCodeStart":328,"sourceCodeEnd":364,"githubUrl":"https://github.com/embassy-rs/embassy/blob/463a07b963419a1bfe61d5d597c44acb810afb8b/embassy-mspm0/src/trng.rs#L328-L364","documentation":"The TRNG is clocked from MCLK and its divider can only bring the input down by the maximum ratio; with MCLK above 160 MHz even the largest division cannot reach the 9.5-20 MHz input range the datasheet requires (L-series TRM 13.2.2), so set_div() aborts. The faulting input is the MCLK frequency configured via sysctl, not a TRNG register setting.","triggerScenarios":"Thrown at embassy-mspm0/src/trng.rs:346 when the library encounters an invalid state.","commonSituations":"See trigger scenarios.","solutions":["Lower MCLK to ≤160 MHz in the clock configuration before initializing the TRNG.","Feed the TRNG from a slower clock tree configuration, or gate MCLK down during TRNG use if the rest of the design tolerates it.","Choose a chip/clock plan where the MCLK-derived TRNG input can be divided into the 9.5-20 MHz range."],"exampleFix":null,"handlingStrategy":"validation","validationCode":null,"typeGuard":null,"tryCatchPattern":null,"preventionTips":[],"tags":[],"backgroundTag":null,"analyzedSha":"463a07b963419a1bfe61d5d597c44acb810afb8b","analyzedAt":"2026-09-10T13:38:26.660Z","contentChangedAt":"2026-09-10T13:38:26.660Z","schemaVersion":2},"datasetVersion":"2026-09-16T04:17:20.429Z"}