{"record":{"id":"fd125f91437aeb5e","repo":"go-delve/delve","slug":"not-valid","errorCode":null,"errorMessage":"not valid","messagePattern":"not valid","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"pkg/proc/linutil/regs_amd64_arch.go","lineNumber":134,"sourceCode":"\nfunc (r *AMD64Registers) BP() uint64 {\n\treturn r.Regs.Rbp\n}\n\n// TLS returns the address of the thread local storage memory segment.\nfunc (r *AMD64Registers) TLS() uint64 {\n\treturn r.Regs.Fs_base\n}\n\n// GAddr returns the address of the G variable if it is known, 0 and false\n// otherwise.\nfunc (r *AMD64Registers) GAddr() (uint64, bool) {\n\treturn 0, false\n}\n\n// LR returns the link register.\nfunc (r *AMD64Registers) LR() uint64 {\n\tpanic(\"not valid\")\n}\n\n// Copy returns a copy of these registers that is guaranteed not to change.\nfunc (r *AMD64Registers) Copy() (proc.Registers, error) {\n\tif r.loadFpRegs != nil {\n\t\terr := r.loadFpRegs(r)\n\t\tr.loadFpRegs = nil\n\t\tif err != nil {\n\t\t\treturn nil, err\n\t\t}\n\t}\n\tvar rr AMD64Registers\n\trr.Regs = &AMD64PtraceRegs{}\n\trr.Fpregset = &amd64util.AMD64Xstate{}\n\t*(rr.Regs) = *(r.Regs)\n\tif r.Fpregset != nil {\n\t\t*(rr.Fpregset) = *(r.Fpregset)\n\t}","sourceCodeStart":116,"sourceCodeEnd":152,"githubUrl":"https://github.com/go-delve/delve/blob/a23773e6c31361e43246bc43a424ee009679b174/pkg/proc/linutil/regs_amd64_arch.go#L116-L152","documentation":"On AMD64 Linux, the ABI has no dedicated link register (return addresses live on the stack), so AMD64Registers.LR() unconditionally panics. The proc.Registers interface includes LR for architectures like ARM64; calling it on AMD64 is always a logic error in the caller.","triggerScenarios":"Calling registers.LR() on an AMD64Registers value, e.g. frame-unwinding or stack-tracing code that assumes a RISC-style link register without checking GOARCH.","commonSituations":"Writing architecture-generic code that reads LR unconditionally; porting tools built on pkg/proc from ARM64 to AMD64; plugins/scripts built on delve internals.","solutions":["Only call LR() when the target architecture has a link register (arm64, etc.)","Use PC() and stack-pointer/frame APIs for unwinding on AMD64","Gate architecture-specific code with runtime.GOARCH or build tags"],"exampleFix":"// before\nlr := regs.LR()\n// after\nvar lr uint64\nif goarch.IsArm64 > 0 { // or runtime.GOARCH == \"arm64\"\n    lr = regs.LR()\n}","handlingStrategy":"type-guard","validationCode":"if runtime.GOARCH == \"amd64\" { /* no LR: do not call */ }","typeGuard":"func hasLinkRegister() bool {\n    switch runtime.GOARCH {\n    case \"arm64\", \"riscv64\", \"loong64\", \"ppc64le\":\n        return true\n    }\n    return false\n}","tryCatchPattern":"defer func() {\n    if r := recover(); r != nil { err = fmt.Errorf(\"LR unavailable: %v\", r) }\n}()","preventionTips":["Check runtime.GOARCH before arch-specific register access","Use PC/CFA-based unwinding on amd64/i386","Keep arch-specific code behind build tags"],"tags":["amd64","registers","panic","not-implemented"],"backgroundTag":"architecture-unsupported-operation","analyzedSha":"a23773e6c31361e43246bc43a424ee009679b174","analyzedAt":"2026-08-31T15:12:45.221Z","schemaVersion":2},"datasetVersion":"2026-08-31T19:17:28.585Z"}