{"id":"e462c046487bd36d","repo":"rust-lang/rust","slug":"vector-type-e462c0","errorCode":null,"errorMessage":"vector type","messagePattern":"vector type","errorType":"panic","errorClass":null,"httpStatus":null,"severity":"error","filePath":"compiler/rustc_codegen_gcc/src/intrinsic/llvm.rs","lineNumber":272,"sourceCode":"            | \"__builtin_ia32_psrlv32hi_mask\"\n            | \"__builtin_ia32_psraw512_mask\"\n            | \"__builtin_ia32_psrawi512_mask\"\n            | \"__builtin_ia32_psrlv16hi_mask\"\n            | \"__builtin_ia32_psrlv8hi_mask\"\n            | \"__builtin_ia32_psrav32hi_mask\"\n            | \"__builtin_ia32_permvarhi512_mask\"\n            | \"__builtin_ia32_pshufb512_mask\"\n            | \"__builtin_ia32_psrav16hi_mask\"\n            | \"__builtin_ia32_psrav8hi_mask\"\n            | \"__builtin_ia32_permvarhi256_mask\"\n            | \"__builtin_ia32_permvarhi128_mask\"\n            | \"__builtin_ia32_maxph128_mask\"\n            | \"__builtin_ia32_maxph256_mask\"\n            | \"__builtin_ia32_minph128_mask\"\n            | \"__builtin_ia32_minph256_mask\" => {\n                let mut new_args = args.to_vec();\n                let arg3_type = gcc_func.get_param_type(2);\n                let vector_type = arg3_type.dyncast_vector().expect(\"vector type\");\n                let zero = builder.context.new_rvalue_zero(vector_type.get_element_type());\n                let num_units = vector_type.get_num_units();\n                let first_arg =\n                    builder.context.new_rvalue_from_vector(None, arg3_type, &vec![zero; num_units]);\n                new_args.push(first_arg);\n                let arg4_type = gcc_func.get_param_type(3);\n                let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1);\n                new_args.push(minus_one);\n                args = new_args.into();\n            }\n            \"__builtin_ia32_dbpsadbw512_mask\"\n            | \"__builtin_ia32_dbpsadbw256_mask\"\n            | \"__builtin_ia32_dbpsadbw128_mask\" => {\n                let mut new_args = args.to_vec();\n                let arg4_type = gcc_func.get_param_type(3);\n                let vector_type = arg4_type.dyncast_vector().expect(\"vector type\");\n                let zero = builder.context.new_rvalue_zero(vector_type.get_element_type());\n                let num_units = vector_type.get_num_units();","sourceCodeStart":254,"sourceCodeEnd":290,"githubUrl":"https://github.com/rust-lang/rust/blob/22057b88b091743bc0fd8d592a9264f0a6951403/compiler/rustc_codegen_gcc/src/intrinsic/llvm.rs#L254-L290","documentation":"This expect(\"vector type\") fires inside the argument-adjustment arm for x86 masked SIMD GCC builtins (the large __builtin_ia32_*512_mask / 256/128 mask family). The backend synthesizes the missing src and mask operands that LLVM intrinsics carry but GCC builtins expose differently; it reads gcc_func.get_param_type(2) (the source operand slot) and calls dyncast_vector() to obtain the vector type so it can construct an all-zero src. If that parameter is not a vector type, dyncast_vector returns None and the expect panics.","triggerScenarios":"Codegen of any LLVM masked SIMD intrinsic that maps to one of the listed __builtin_ia32_*512_mask / _256_mask / _128_mask builtins (e.g. AVX-512 packed arithmetic, pack/unpack, permute, compare-mask) when the GCC builtin's 3rd parameter is not reported as a vector type by libgccjit. Triggered by std::arch::x86_64 SIMD intrinsics in the masked variants.","commonSituations":"Using std::arch::x86_64 / avx512f masked intrinsics; GCC/libgccjit version mismatch where the builtin signature or type-kind changed; building SIMD-heavy crates (e.g. wide, packed_simd) against a libgccjit that does not expose the expected vector type for the src parameter.","solutions":["Upgrade libgccjit (and GCC) to a version whose __builtin_ia32_*_mask builtins expose a vector type at parameter index 2.","Verify the GCC target features (avx512f/avx512bw/etc.) are enabled for the builtin being called; a missing feature can alter the resolved builtin signature.","Disable the affected AVX-512 masked intrinsic in source (drop the mask argument variant, use the unmasked intrinsic) to avoid the adjustment arm.","Report upstream to rustc_codegen_gcc with the exact builtin name and libgccjit version."],"exampleFix":"// before\nlet r = _mm512_add_epi32_mask(a, b, mask);\n// after (use the unmasked variant when libgccjit mis-reports the src param type)\nlet r = _mm512_add_epi32(a, b);","handlingStrategy":"fallback","validationCode":"# The panic is in the AVX-512 masked-builtin shim (arg3 must be a vector type).\n# Fail fast if the crate uses 512-bit masked SIMD intrinsics under the GCC backend.\nif rg --type rust -n '_mm512_|__builtin_ia32_.*512_mask|target_feature\\s*=\\s*\"avx512' src/; then\n  echo 'ERROR: AVX-512 masked intrinsics trigger GCC backend panic (llvm.rs:272)' >&2\n  exit 1\nfi","typeGuard":"// Compile-time cfg gate: AVX-512 masked SIMD requires the LLVM backend.\n#[cfg(all(feature = \"gcc-backend\", any(target_feature = \"avx512f\", target_feature = \"avx512bw\")))]\ncompile_error!(\n    \"AVX-512 masked intrinsics are not supported by the GCC backend; build without 'gcc-backend' or drop avx512 target-features\"\n);","tryCatchPattern":"set +e\nRUSTFLAGS='-C codegen-backend=gcc' cargo build --release 2>gcc_build.log\nstatus=$?\nset -e\nif [ $status -ne 0 ]; then\n  echo 'GCC backend failed (llvm.rs:272 avx512 vector); rebuilding with LLVM backend' >&2\n  cargo build --release\nfi","preventionTips":["Avoid _mm512_* masked intrinsics (psraw/psrlv/pshufb/permvar families) when compiling with the GCC backend.","Gate SIMD hot paths behind cfg and select the LLVM backend for SIMD-heavy crates.","Lower target-feature requirements (drop avx512f/avx512bw) when using the GCC backend.","Keep an LLVM-backend CI lane so SIMD regressions are caught before the GCC lane runs."],"tags":["rust","codegen","gcc","libgccjit","simd","avx512","x86"],"analyzedSha":"22057b88b091743bc0fd8d592a9264f0a6951403","analyzedAt":"2026-08-03T08:09:25.915Z","schemaVersion":2}