embassy-rs/embassy · error

DMA address error

Error message

DMA address error

What it means

Panic in the MSPM0 DMA interrupt handler on_irq: the DMA mixed interrupt-status register reports an address error (ADDRERR), meaning the DMA controller attempted a transfer using an address outside a valid memory region or with illegal alignment for the transfer width, and the bus faulted. Because the IRQ handler is shared across channels, the specific failing channel is not identified here — the code notes this as a known limitation. This is a hardware-error sentinel: the input at fault is the configured source/destination address (or its alignment) of one of the active DMA channels.

Solutions

1. Verify every active DMA channel's source and destination addresses point to valid, mapped memory for the transfer width
2. Check alignment: buffer addresses must match the transfer width/data-alignment requirements of the channel
3. Ensure buffers live in RAM regions the DMA can access (not flash or peripheral-reserved space) and are not moved after arming
4. Review channel setup order so a channel is never armed with uninitialized address registers

When it happens

Trigger: Thrown at embassy-mspm0/src/dma.rs:647 when the library encounters an invalid state.

Common situations: See trigger scenarios.

AI-assisted analysis of embassy-rs/embassy@463a07b963 (2026-09-10). Data as JSON: /api/errors/a84cf64d93380be8. Report an issue: GitHub.

Appendix: source

Thrown at embassy-mspm0/src/dma.rs:647

macro_rules! impl_full_dma_channel {
    ($instance: ident, $num: expr) => {
        impl_dma_channel!($instance, $num);

        impl crate::dma::FullChannelInstance for crate::peripherals::$instance {}
    };
}

fn on_irq(dma: pac::dma::Dma) {
    use crate::BitIter;

    let events = dma.int_event(0);
    let mis = events.mis().read();

    // TODO: Handle DATAERR and ADDRERR? However we do not know which channel causes an error.
    if mis.dataerr() {
        panic!("DMA data error");
    } else if mis.addrerr() {
        panic!("DMA address error")
    }

    // Ignore preirq interrupts (values greater than 16).
    for i in BitIter(mis.0 & 0x0000_FFFF) {
        if let Some(state) = STATE.get(i as usize) {
            state.waker.wake();

            // Notify the future that the counter size hit zero
            events.imask().modify(|w| {
                w.set_ch(i as usize, false);
            });
        }
    }
}

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