sgl-project/sglang · error · ValueError

{name} must live on CUDA

Error message

{name} must live on CUDA

What it means

Raised when an auxiliary metadata tensor (e.g. dq_write_order) is not on CUDA while the rest of the block-sparse bundle is. The kernel reads it from GPU memory.

Source

Thrown at python/sglang/kernels/ops/attention/flash_attn/cute/block_sparsity.py:285

    return expanded_cnt, expanded_idx


def _check_and_expand_metadata_tensor(
    name: str,
    tensor: torch.Tensor | None,
    expected_shape: Tuple[int, ...],
    context: str | None,
    hint: str | Callable[[], str] | None,
    device: torch.device,
) -> torch.Tensor | None:
    if tensor is None:
        return None
    if tensor.dtype != torch.int32:
        raise ValueError(f"{name} must have dtype torch.int32")
    if tensor.device != device:
        raise ValueError(f"{name} must be on the same device as block sparse tensors")
    if not tensor.is_cuda:
        raise ValueError(f"{name} must live on CUDA")
    return _expand_sparsity_tensor(tensor, expected_shape, name, context, hint)


def get_block_sparse_expected_shapes(
    batch_size: int,
    num_head: int,
    seqlen_q: int,
    seqlen_k: int,
    m_block_size: int,
    n_block_size: int,
    q_stage: int,
) -> Tuple[Tuple[int, int, int], Tuple[int, int, int, int]]:
    """Return (expected_count_shape, expected_index_shape) for block sparse normalization."""
    m_block_size_effective = q_stage * m_block_size
    expected_m_blocks = ceildiv(seqlen_q, m_block_size_effective)
    expected_n_blocks = ceildiv(seqlen_k, n_block_size)
    expected_count_shape = (batch_size, num_head, expected_m_blocks)
    expected_index_shape = (batch_size, num_head, expected_m_blocks, expected_n_blocks)

View on GitHub (pinned to 0132848349)

Solutions

1. dq_write_order = dq_write_order.cuda()
2. Create it directly on the target CUDA device with device='cuda'

Example fix

// before
order = torch.arange(M, dtype=torch.int32)
// after
order = torch.arange(M, dtype=torch.int32, device='cuda')

assert dq_write_order is None or dq_write_order.is_cuda

When it happens

Trigger: Passing a CPU dq_write_order tensor (e.g. from torch.arange on CPU) into normalize_block_sparse_tensors.

Common situations: Generating dq_write_order during CPU-side mask preparation and forgetting the .cuda() transfer.

Related errors

• {name}_block tensors must live on CUDA
• {name}_block_cnt and {name}_block_idx must be on the same de
• {name} must have dtype torch.int32
• {name} must be on the same device as block sparse tensors
• q must be a CUDA tensor

AI-assisted analysis of sgl-project/sglang@0132848349 (2026-08-28). Data as JSON: /api/errors/a232bac1d99d90ab. Report an issue: GitHub.