embassy-rs/embassy · error

AUDIOCLK not supported yet

Error message

AUDIOCLK not supported yet

What it means

embassy-stm32's STM32WBA RCC driver does not implement the external AUDIOCLK input as an SAI1 audio clock source. Selecting config.mux.sai1sel = Sai1sel::Audioclk panics with 'AUDIOCLK not supported yet' — a driver limitation, not a hardware fault.

Solutions

1. Select Sai1sel::Hsi, Sai1sel::Pll1Q, or Sai1sel::Pll1P instead, tuning PLL1 to the required audio clock frequency
2. Upgrade embassy-stm32 in case AUDIOCLK support for WBA has been added upstream
3. Patch the driver to implement the Audioclk arm if the external clock is required

Example fix

// before
config.mux.sai1sel = mux::Sai1sel::AUDIOCLK; // panic: not supported
// after
config.mux.sai1sel = mux::Sai1sel::PLL1_Q; // tune PLL1.Q to e.g. 12.288 MHz for 48 kHz audio

assert!(!matches!(config.mux.sai1sel, mux::Sai1sel::AUDIOCLK),
    "AUDIOCLK SAI1 source not implemented in embassy-stm32 WBA driver");

fn sai1sel_implemented(sel: &mux::Sai1sel) -> bool {
    !matches!(sel, mux::Sai1sel::Sys | mux::Sai1sel::Audioclk)
}

When it happens

Trigger: rcc init with config.mux.sai1sel = Sai1sel::Audioclk on an STM32WBA target with sai_v4_2pdm enabled, typically to drive SAI1 from an external audio master clock.

Common situations: Boards with an external audio codec clock wired to the AUDIOCLK pins; porting SAI clock mux settings from another family/driver where Audioclk is supported.

Related errors

• SYS not supported yet
• Invalid ahb5_pre for HSI/HSE sysclk: only DIV1 and DIV2 are…
• cannot select OTG_HS reference clock with source frequency…
• The LCD driver needs the RTC/LCD clock to be running
• if PLL source is HSI, PLL prediv must be 2.

AI-assisted analysis of embassy-rs/embassy@463a07b963 (2026-09-10). Data as JSON: /api/errors/b0ad9cf99c2c8ed1. Report an issue: GitHub.

Appendix: source

Thrown at embassy-stm32/src/rcc/wba.rs:426

            _ => panic!(
                "cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz",
                clk_val
            ),
        },
        None => Usbrefcksel::Mhz24,
    };
    #[cfg(all(stm32wba, peri_usb_otg_hs))]
    SYSCFG.otghsphycr().modify(|w| {
        w.set_clksel(usb_refck_sel);
    });

    #[cfg(sai_v4_2pdm)]
    let audioclk = match config.mux.sai1sel {
        Sai1sel::Hsi => Some(HSI_FREQ),
        Sai1sel::Pll1Q => Some(pll1.q.expect("PLL1.Q not configured")),
        Sai1sel::Pll1P => Some(pll1.p.expect("PLL1.P not configured")),
        Sai1sel::Sys => panic!("SYS not supported yet"),
        Sai1sel::Audioclk => panic!("AUDIOCLK not supported yet"),
        _ => None,
    };

    let lsi = config.ls.lsi.then_some(LSI_FREQ);
    let lse = config.ls.lse.map(|c| c.frequency);

    // Disable HSI if not used
    if !config.hsi {
        assert!(
            config.mux.rngsel != mux::Rngsel::Hsi,
            "RNG is configured to use HSI but HSI is disabled"
        );
        RCC.cr().modify(|w| w.set_hsion(false));
    }

    config.mux.init();

    set_clocks!(

View on GitHub (pinned to 463a07b963)