embassy-rs/embassy · error

MCLK frequency > 160 MHz is not compatible with the TRNG

Error message

MCLK frequency {} > 160 MHz is not compatible with the TRNG

What it means

The TRNG is clocked from MCLK and its divider can only bring the input down by the maximum ratio; with MCLK above 160 MHz even the largest division cannot reach the 9.5-20 MHz input range the datasheet requires (L-series TRM 13.2.2), so set_div() aborts. The faulting input is the MCLK frequency configured via sysctl, not a TRNG register setting.

Solutions

1. Lower MCLK to ≤160 MHz in the clock configuration before initializing the TRNG.
2. Feed the TRNG from a slower clock tree configuration, or gate MCLK down during TRNG use if the rest of the design tolerates it.
3. Choose a chip/clock plan where the MCLK-derived TRNG input can be divided into the 9.5-20 MHz range.

When it happens

Trigger: Thrown at embassy-mspm0/src/trng.rs:346 when the library encounters an invalid state.

Common situations: See trigger scenarios.

AI-assisted analysis of embassy-rs/embassy@463a07b963 (2026-09-10). Data as JSON: /api/errors/fcb93d3618c9f428. Report an issue: GitHub.

Appendix: source

Thrown at embassy-mspm0/src/trng.rs:346

        });
    }

    fn power_on(&mut self) {
        regs().gprcm().pwren().write(|w| {
            w.set_key(PwrenKey::Key);
            w.set_enable(true);
        });
    }

    fn power_off(&mut self) {
        regs().gprcm().pwren().write(|w| w.set_key(PwrenKey::Key));
    }

    fn set_div(&mut self) {
        // L-series TRM 13.2.2: The TRNG is derived from MCLK. Datasheets specify 9.5-20 MHz range.
        let freq = crate::sysctl::mclk_frequency();
        let ratio = if freq > 160_000_000 {
            panic!("MCLK frequency {} > 160 MHz is not compatible with the TRNG", freq)
        } else if freq >= 80_000_000 {
            Ratio::DivBy8
        } else if freq >= 60_000_000 {
            Ratio::DivBy6
        } else if freq >= 40_000_000 {
            Ratio::DivBy4
        } else if freq >= 20_000_000 {
            Ratio::DivBy2
        } else if freq >= 9_500_000 {
            Ratio::DivBy1
        } else {
            panic!("MCLK frequency {} < 9.5 MHz is not compatible with the TRNG", freq)
        };
        regs().clkdiv().write(|w| w.set_ratio(ratio));
    }

    fn set_decim_rate(&mut self) {
        regs().ctl().modify(|w| w.set_decim_rate(self.decim_rate));

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