embassy-rs/embassy · error

HSE is not ready to be selected as CPU clock source

Error message

HSE is not ready to be selected as CPU clock source

What it means

On STM32N6, before switching the CPU clock to HSE, the code checks `RCC.sr().hserdy()`. If the external high-speed oscillator is not running and stable, selecting it as the CPU clock would fail, so the library panics.

Solutions

  1. Configure HSE in the rcc config (`hse: Some(Hse { mode, crystal/bypass freq, ... })`) so it is enabled and awaited ready.
  2. If the board has no HSE crystal, use `bypass` with an external clock or switch `cpu` to Hsi/Msi/Ic1.
  3. Verify hardware: crystal frequency, load capacitors, and bypass mode match the config.

Example fix

// before
rcc: RccConfig { cpu: CpuClk::Hse, ..Default::default() }, // hse never enabled
// after
rcc: RccConfig {
    hse: Some(Hse { freq: MegaHertz::new(24), mode: HseMode::Oscillator }),
    cpu: CpuClk::Hse,
    ..Default::default()
},
Defensive patterns

Strategy: validation

Validate before calling

if config.rcc.cpu == CpuClk::Hse && config.rcc.hse.is_none() {
    panic!("CpuClk::Hse requires an hse config in rcc");
}

Type guard

fn hse_ready_for_cpu(rcc: &RccConfig) -> bool {
    rcc.cpu != CpuClk::Hse || rcc.hse.is_some()
}

Prevention

When it happens

Trigger: Setting `config.cpu = CpuClk::Hse` while `hserdy()` is false — HSE not enabled in config (`hse: None`), wrong crystal/bypass mode, or the crystal not oscillating on the board.

Common situations: Board lacking the HSE crystal while config selects HSE; incorrect hse bypass setting for an external clock; HSE startup failure due to load capacitor issues.

Understand the failure class

Background: "Invalid state transition" errors: "status must be X, actually Y", "already rejected/charging/uninstalled", "cannot ... while running" — what they mean when a library rejects your call — this error's family across 31 libraries.

Related errors


AI-assisted analysis of embassy-rs/embassy@463a07b963 (2026-09-10). Data as JSON: /api/errors/eeb58f2f943a7cf0. Report an issue: GitHub.

Appendix: source

Thrown at embassy-stm32/src/rcc/n6.rs:357

        if config.apb4 > w.ppre4() {
            debug!("  - APB4");
            w.set_ppre4(config.apb4);
        }
        if config.apb5 > w.ppre5() {
            debug!("  - APB5");
            w.set_ppre5(config.apb5);
        }
        if config.ahb > w.hpre() {
            debug!("  - AHB");
            w.set_hpre(config.ahb);
        }
    });
    // cpuclk
    debug!("configuring cpuclk");
    match config.cpu {
        CpuClk::Hsi if !RCC.sr().read().hsirdy() => panic!("HSI is not ready to be selected as CPU clock source"),
        CpuClk::Msi if !RCC.sr().read().msirdy() => panic!("MSI is not ready to be selected as CPU clock source"),
        CpuClk::Hse if !RCC.sr().read().hserdy() => panic!("HSE is not ready to be selected as CPU clock source"),
        CpuClk::Ic1 if !ic_enabled(1) => panic!("IC1 is not ready to be selected as CPU clock source"),
        _ => {}
    }
    // set source
    let cpusw = Cpusw::from_bits(config.cpu.to_bits());
    RCC.cfgr().modify(|w| w.set_cpusw(cpusw));
    // wait for changes to take effect
    while RCC.cfgr().read().cpusws() != Cpusws::from_bits(config.cpu.to_bits()) {}

    // sysclk
    debug!("configuring sysclk");
    match config.sys {
        SysClk::Hsi if !RCC.sr().read().hsirdy() => panic!("HSI is not ready to be selected as system clock source"),
        SysClk::Msi if !RCC.sr().read().msirdy() => panic!("MSI is not ready to be selected as system clock source"),
        SysClk::Hse if !RCC.sr().read().hserdy() => panic!("HSE is not ready to be selected as system clock source"),
        SysClk::Ic2 if !ic_enabled(2) || !ic_enabled(6) || !ic_enabled(11) => panic!(
            "IC2 is not ready to be selected as system clock source (make sure that IC6 and IC11 were configured as well)"
        ),

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