embassy-rs/embassy · error

HSI is not ready to be selected as system clock source

Error message

HSI is not ready to be selected as system clock source

What it means

During clock-tree init the requested CpuClk::Hsi source is checked against RCC's hsirdy status bit before switching cpuclk; HSI has not stabilized or was not enabled before selection, so switching the CPU clock to it would be unsafe and the guard panics. This is the HSI arm of the same readiness match that guards MSI/HSE/IC1.

Solutions

1. Enable HSI in the rcc config (`hsi: true`) so it is ready before the sysclk switch.
2. Or change `config.sys` to a source that is ready (Hse/Msi/Ic2).
3. Review the cpu/sys config pair so both use sources that are actually enabled.

Example fix

// before
rcc: RccConfig { sys: SysClk::Hsi, ..Default::default() }, // hsi disabled
// after
rcc: RccConfig { hsi: true, sys: SysClk::Hsi, ..Default::default() },

if config.rcc.sys == SysClk::Hsi && !config.rcc.hsi {
    panic!("SysClk::Hsi requires hsi: true in rcc config");
}

fn sys_source_configured(sys: SysClk, rcc: &RccConfig) -> bool {
    match sys {
        SysClk::Hsi => rcc.hsi,
        SysClk::Hse => rcc.hse.is_some(),
        SysClk::Msi => rcc.msi.is_some(),
        SysClk::Ic2 => rcc.ics.get(1).map_or(false, |ic| ic.is_some()),
    }
}

When it happens

Trigger: Setting `config.sys = SysClk::Hsi` while `hsirdy()` is false — HSI not enabled in the rcc config or disabled before the sysclk switch (note: the CPU-clock switch has already completed at this point).

Common situations: Configuring sysclk to HSI but leaving `hsi: false`; an earlier CPU-clock selection that turned HSI off; reinit flows where HSI was never re-enabled.

Understand the failure class

Background: "Invalid state transition" errors: "status must be X, actually Y", "already rejected/charging/uninstalled", "cannot ... while running" — what they mean when a library rejects your call — this error's family across 31 libraries.

Related errors

• HSI is not ready to be selected as CPU clock source
• MSI is not ready to be selected as system clock source
• HSE is not ready to be selected as system clock source
• IC source was set to PLL , but it is not currently enabled
• MSI is not ready to be selected as CPU clock source

AI-assisted analysis of embassy-rs/embassy@463a07b963 (2026-09-10). Data as JSON: /api/errors/ecc52ea41ac1b746. Report an issue: GitHub.

Appendix: source

Thrown at embassy-stm32/src/rcc/n6.rs:370

    // cpuclk
    debug!("configuring cpuclk");
    match config.cpu {
        CpuClk::Hsi if !RCC.sr().read().hsirdy() => panic!("HSI is not ready to be selected as CPU clock source"),
        CpuClk::Msi if !RCC.sr().read().msirdy() => panic!("MSI is not ready to be selected as CPU clock source"),
        CpuClk::Hse if !RCC.sr().read().hserdy() => panic!("HSE is not ready to be selected as CPU clock source"),
        CpuClk::Ic1 if !ic_enabled(1) => panic!("IC1 is not ready to be selected as CPU clock source"),
        _ => {}
    }
    // set source
    let cpusw = Cpusw::from_bits(config.cpu.to_bits());
    RCC.cfgr().modify(|w| w.set_cpusw(cpusw));
    // wait for changes to take effect
    while RCC.cfgr().read().cpusws() != Cpusws::from_bits(config.cpu.to_bits()) {}

    // sysclk
    debug!("configuring sysclk");
    match config.sys {
        SysClk::Hsi if !RCC.sr().read().hsirdy() => panic!("HSI is not ready to be selected as system clock source"),
        SysClk::Msi if !RCC.sr().read().msirdy() => panic!("MSI is not ready to be selected as system clock source"),
        SysClk::Hse if !RCC.sr().read().hserdy() => panic!("HSE is not ready to be selected as system clock source"),
        SysClk::Ic2 if !ic_enabled(2) || !ic_enabled(6) || !ic_enabled(11) => panic!(
            "IC2 is not ready to be selected as system clock source (make sure that IC6 and IC11 were configured as well)"
        ),
        _ => {}
    }
    // switch the system bus clock
    let syssw = Syssw::from_bits(config.sys.to_bits());
    RCC.cfgr().modify(|w| w.set_syssw(syssw));
    // wait for changes to be applied
    while RCC.cfgr().read().syssws() != Syssws::from_bits(config.sys.to_bits()) {}

    // decreasing dividers
    debug!("configuring decreasing pclk dividers");
    RCC.cfgr2().modify(|w| {
        if config.ahb < w.hpre() {
            debug!("  - AHB");

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