embassy-rs/embassy · error

PLL1.P not configured

Error message

PLL1.P not configured

What it means

Same guard as PLL1.Q but for the P output: in STM32WBA rcc `init`, selecting `sai1sel: Sai1sel::Pll1P` runs `pll1.p.expect("PLL1.P not configured")`, panicking when PLL1's P output was not configured. SAI1 muxed to PLL1P needs that PLL output to exist in the clock tree.

Solutions

1. Configure `config.pll1.p` with the required frequency and divider for the audio clock
2. Switch `sai1sel` to a configured source (Hsi or Pll1Q if set up)
3. Cross-check the PLLP output against the SAI sample-rate clock requirement

Example fix

// before
let config = rcc::Config { mux: rcc::mux::Sai1sel::Pll1P, pll1: Pll1 { p: None, .. } };
// after
let config = rcc::Config {
    mux: rcc::mux::Sai1sel::Pll1P,
    pll1: Pll1 { p: Some(PllConfig { div: 8, freq: Hertz(12_288_000) }), .. },
    ..
};

if config.mux.sai1sel == rcc::mux::Sai1sel::Pll1P && config.pll1.p.is_none() {
    panic!("sai1sel=Pll1P requires config.pll1.p to be configured");
}

When it happens

Trigger: Setting `config.mux.sai1sel = Sai1sel::Pll1P` while `config.pll1.p` is `None` (P frequency/div unset).

Common situations: Audio (SAI/I2S) init where PLL1 was configured only for SYSCLK via Q, leaving P undefined; templates that enable the PLL1P mux by default without enabling the PLL output.

Understand the failure class

Background: "is required", "must be set", "missing required field": configuration validation errors across open-source libraries — this error's family across 36 libraries.

Related errors

• PLL1.Q not configured
• must not set PllSource::Disable
• must not select PLL source as DISABLE
• PLL is unavailable in voltage range 2
• if PLL source is HSI, PLL prediv must be 2.

AI-assisted analysis of embassy-rs/embassy@463a07b963 (2026-09-10). Data as JSON: /api/errors/a9a042994d0965ad. Report an issue: GitHub.

Appendix: source

Thrown at embassy-stm32/src/rcc/wba.rs:424

            Hertz(26_000_000) => Usbrefcksel::Mhz26,
            Hertz(32_000_000) => Usbrefcksel::Mhz32,
            _ => panic!(
                "cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz",
                clk_val
            ),
        },
        None => Usbrefcksel::Mhz24,
    };
    #[cfg(all(stm32wba, peri_usb_otg_hs))]
    SYSCFG.otghsphycr().modify(|w| {
        w.set_clksel(usb_refck_sel);
    });

    #[cfg(sai_v4_2pdm)]
    let audioclk = match config.mux.sai1sel {
        Sai1sel::Hsi => Some(HSI_FREQ),
        Sai1sel::Pll1Q => Some(pll1.q.expect("PLL1.Q not configured")),
        Sai1sel::Pll1P => Some(pll1.p.expect("PLL1.P not configured")),
        Sai1sel::Sys => panic!("SYS not supported yet"),
        Sai1sel::Audioclk => panic!("AUDIOCLK not supported yet"),
        _ => None,
    };

    let lsi = config.ls.lsi.then_some(LSI_FREQ);
    let lse = config.ls.lse.map(|c| c.frequency);

    // Disable HSI if not used
    if !config.hsi {
        assert!(
            config.mux.rngsel != mux::Rngsel::Hsi,
            "RNG is configured to use HSI but HSI is disabled"
        );
        RCC.cr().modify(|w| w.set_hsion(false));
    }

    config.mux.init();

View on GitHub (pinned to 463a07b963)