Direct CSR command sending is not implemented for RISC-V yet

Error message

Direct CSR command sending is not implemented for RISC-V yet

What it means

direct_csr_send_init_command sends a direct CSR command to the PSRAM over the QMI interface using inline assembly; only the ARM path is implemented, and the riscv32 path is unconditionally unimplemented. Any direct-CSR setup on a RISC-V RP2350 build panics.

Solutions

Compile for the ARM (thumbv8m.main-none-eabihf) target where the asm path exists
Implement the riscv32 asm sequence mirroring the ARM version
Avoid direct CSR commands on RISC-V and configure QMI via register writes instead
Gate the CSR init behind a cfg so RISC-V builds skip it

Example fix

// before
psram::Psram::new(p.QMI, p.PIN_0, ...); // on riscv32 target
// after
# build for thumbv8m.main-none-eabihf instead

Defensive patterns

Strategy: type-guard

Validate before calling

#[cfg(target_arch = "riscv32")] compile_error!("direct CSR PSRAM init unsupported on riscv32");

Type guard

const CSR_DIRECT_SUPPORTED: bool = cfg!(not(target_arch = "riscv32"));

Prevention

Avoid direct-CSR PSRAM init on RISC-V cores
Use ARM target builds when QMI direct commands are needed

When it happens

Trigger: Calling direct_csr_send_init_command during PSRAM initialization when compiled with target_arch = "riscv32".

Common situations: Initializing APS6404L PSRAM on RP2350 using the RISC-V cores instead of the ARM cores.

Understand the failure class

Background: "unsupported platform" / "not supported on this platform" errors: what they mean and how to fix them — this error's family across 47 libraries.

Related errors

AI-assisted analysis of embassy-rs/embassy@463a07b963 (2026-09-10). Data as JSON: /api/errors/f7ce3e632855f8e9. Report an issue: GitHub.

Appendix: source

Thrown at embassy-rp/src/psram.rs:685

        "bne 2b",                        // Branch if busy

        // Disable Direct CSR
        "mov {temp}, #0",
        "str {temp}, [{base}, #0]",      // Clear DIRECT_CSR register

        // Full memory barrier to ensure no prefetching
        "dmb",
        "dsb",
        "isb",
        base = out(reg) _,
        temp = out(reg) _,
        clkdiv = in(reg) config.init_clkdiv as u32,
        enter_quad_cmd = in(reg) u32::from(init_cmd),
        options(nostack),
        );

        #[cfg(target_arch = "riscv32")]
        unimplemented!("Direct CSR command sending is not implemented for RISC-V yet");
    }
}

View on GitHub (pinned to 463a07b963)