embassy-rs/embassy · error

MSI is not ready to be selected as CPU clock source

Error message

MSI is not ready to be selected as CPU clock source

What it means

During clock-tree init the requested CpuClk::Msi source is checked against RCC's msirdy status bit before switching cpuclk; MSI has not finished stabilizing (or was never enabled), and switching anyway could stall the core, so the guard panics. The input at fault is the MSI configuration/startup delay, not the RCC registers themselves.

Solutions

  1. Enable/configure MSI in the rcc config (`msi: Some(MsiConfig...)`) so it runs and is ready.
  2. Or select a ready CPU source (Hsi/Hse/Ic1) in `config.cpu`.
  3. Confirm no other config path disables MSI before the CPU switch.

Example fix

// before
rcc: RccConfig { cpu: CpuClk::Msi, ..Default::default() }, // msi not configured
// after
rcc: RccConfig { msi: Some(MsiConfig::default()), cpu: CpuClk::Msi, ..Default::default() },
Defensive patterns

Strategy: validation

Validate before calling

if config.rcc.cpu == CpuClk::Msi && config.rcc.msi.is_none() {
    panic!("CpuClk::Msi requires an msi config in rcc");
}

Type guard

fn msi_ready_for_cpu(rcc: &RccConfig) -> bool {
    rcc.cpu != CpuClk::Msi || rcc.msi.is_some()
}

Prevention

When it happens

Trigger: Setting `config.cpu = CpuClk::Msi` while `msirdy()` is false — MSI not enabled/configured in the rcc config, or its range/trim config failing to bring it up before the switch.

Common situations: Using MSI as CPU source without an msi config entry; disabling MSI elsewhere in config while still selecting it as cpu; reinit where MSI was turned off.

Understand the failure class

Background: "Invalid state transition" errors: "status must be X, actually Y", "already rejected/charging/uninstalled", "cannot ... while running" — what they mean when a library rejects your call — this error's family across 31 libraries.

Related errors

AI-assisted analysis of embassy-rs/embassy@463a07b963 (2026-09-10). Data as JSON: /api/errors/61fa032098818ff4. Report an issue: GitHub.

Appendix: source

Thrown at embassy-stm32/src/rcc/n6.rs:356

        }
        if config.apb4 > w.ppre4() {
            debug!("  - APB4");
            w.set_ppre4(config.apb4);
        }
        if config.apb5 > w.ppre5() {
            debug!("  - APB5");
            w.set_ppre5(config.apb5);
        }
        if config.ahb > w.hpre() {
            debug!("  - AHB");
            w.set_hpre(config.ahb);
        }
    });
    // cpuclk
    debug!("configuring cpuclk");
    match config.cpu {
        CpuClk::Hsi if !RCC.sr().read().hsirdy() => panic!("HSI is not ready to be selected as CPU clock source"),
        CpuClk::Msi if !RCC.sr().read().msirdy() => panic!("MSI is not ready to be selected as CPU clock source"),
        CpuClk::Hse if !RCC.sr().read().hserdy() => panic!("HSE is not ready to be selected as CPU clock source"),
        CpuClk::Ic1 if !ic_enabled(1) => panic!("IC1 is not ready to be selected as CPU clock source"),
        _ => {}
    }
    // set source
    let cpusw = Cpusw::from_bits(config.cpu.to_bits());
    RCC.cfgr().modify(|w| w.set_cpusw(cpusw));
    // wait for changes to take effect
    while RCC.cfgr().read().cpusws() != Cpusws::from_bits(config.cpu.to_bits()) {}

    // sysclk
    debug!("configuring sysclk");
    match config.sys {
        SysClk::Hsi if !RCC.sr().read().hsirdy() => panic!("HSI is not ready to be selected as system clock source"),
        SysClk::Msi if !RCC.sr().read().msirdy() => panic!("MSI is not ready to be selected as system clock source"),
        SysClk::Hse if !RCC.sr().read().hserdy() => panic!("HSE is not ready to be selected as system clock source"),
        SysClk::Ic2 if !ic_enabled(2) || !ic_enabled(6) || !ic_enabled(11) => panic!(
            "IC2 is not ready to be selected as system clock source (make sure that IC6 and IC11 were configured as well)"

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